TMS320DM643 datasheet(142/160 Pages) TI

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MRCLK (Input)

MRXD3−MRXD0,

MRXDV, MRXER (Inputs)

MTCLK (Input)

MTXD3−MTXD0,

MTXEN (Outputs)

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Table 5-66. Timing Requirements for EMAC MII Receive 10/100 Mbit/s

(1) (see Figure 5-59)

–500

–600

NO.

UNIT

MIN

MAX

tsu(MRXD-MRCLKH)

Setup time, receive selected signals valid before MRCLK high

th(MRCLKH-MRXD)

Hold time, receive selected signals valid after MRCLK high

(1)

Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.

MRXD3–MRXD0 is driven by the PHY on the falling edge of MRCLK. MRXD3–MRXD0 timing must be

met during clock periods when MRXDV is asserted. MRXDV is asserted and deasserted by the PHY on

the falling edge of MRCLK. MRXER is driven by the PHY on the falling edge of MRCLK (xx = 00–01).

Figure 5-59. EMAC Receive Interface Timing

Table 5-67. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit

10/100 Mbit/s

(1) (see Figure 5-60)

–500

–600

NO.

UNIT

MIN

MAX

td(MTCLKH-MTXD)

Delay time, MTCLK high to transmit selected signals valid

(1)

Transmit selected signals include: MTXD3–MTXD0, and MTXEN.

MTXD3–MTXD0 is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted

and deasserted by the reconciliation sublayer synchronous to the MTCLK rising edge.

Figure 5-60. EMAC Transmit Interface Timing

142

DM643 Peripheral Information and Electrical Specifications

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