TMS320DM643 datasheet(105/160 Pages) TI

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5.9.3

McASP0 Electrical Data/Timing

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Table 5-30. McASP0 Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

01B4 C28C

RBUF3

Receive Buffer for Serializer 3

01B4 C290

RBUF4

Receive Buffer for Serializer 4

01B4 C294

RBUF5

Receive Buffer for Serializer 5

01B4 C298

RBUF6

Receive Buffer for Serializer 6

01B4 C29C

RBUF7

Receive Buffer for Serializer 7

01B4 C2A0 – 01B4 FFFF

–

Reserved

Table 5-31. McASP0 Data Registers

HEX ADDRESS RANGE

ACRONYM

COMMENTS

(Used when RSEL or XSEL

McASPx receive buffers or McASPx transmit buffers via

bits = 0 [these bits are located

3C00 0000 – 3C0F FFFF

RBUF/XBUFx

the Peripheral Data Bus.

in the RFMT or XFMT registers,

respectively].)

5.9.3.1

Multichannel Audio Serial Port (McASP) Timing

Table 5-32. Timing Requirements for McASP (see Figure 5-33 and Figure 5-34)

–500

–600

NO.

UNIT

MIN

MAX

tc(AHCKRX)

Cycle time, AHCLKR/X

tw(AHCKRX)

Pulse duration, AHCLKR/X high or low

tc(CKRX)

Cycle time, ACLKR/X

ACLKR/X ext

tw(CKRX)

Pulse duration, ACLKR/X high or low

ACLKR/X ext

16.5

ACLKR/X int

tsu(FRX-CKRX)

Setup time, AFSR/X input valid before ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

th(CKRX-FRX)

Hold time, AFSR/X input valid after ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

tsu(AXR-CKRX)

Setup time, AXR input valid before ACLKR/X latches data

ACLKR/X ext

ACLKR/X int

th(CKRX-AXR)

Hold time, AXR input valid after ACLKR/X latches data

ACLKR/X ext

DM643 Peripheral Information and Electrical Specifications

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