DSP56857 datasheet(178/662 Pages) FREESCALE

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Clocks

5685X Digital Signal Controller User Manual, Rev. 4

7-10

Freescale Semiconductor

7.9.3 COP Counter Register (COPCTR)

Figure 7-6. COP Counter Register (COPCTR)

See Programmer’s Sheet on Appendix page B-20

7.9.3.1 COP Count (COUNT)—Bits 15–0

This is the current value of the COP counter as it counts down from the time-out value to zero. A

reset is issued when this count reaches zero.

7.9.3.2 COP Service (SERVICE)—Bits 15–0

When enabled, the COP requires a service sequence be performed periodically in order to clear

the COP counter and prevent a reset from being issued. This routine consists of writing $5555 to

the COPCTR followed by writing $AAAA before the time-out period expires. The writes to

COPCTR must be performed in the correct order, but any number of other instructions, and

writes to other registers, may be executed between the two writes.

7.10 Clocks

The COP timer base is the oscillator clock divided by a fixed prescalar value. The prescalar

divisor for this chip is 128. All register timing is with regard to the IPBus clock.

7.11 Resets

Any system reset forces all registers to their reset state, clearing the RST signal when it is

asserted. The counter will be loaded with its maximum value of $FFFF, but it will not start when

Reset is released because the CEN bit is disabled by default.

7.12 Interrupts

The COP module does not generate any interrupts. It does generate the RST signal when the

counter reaches a value of $0000, causing a chip wide reset.

Base + $2

Read

COUNT

Write

SERVICE

Reset

1111

11111

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