DSP56857 datasheet(176/662 Pages) FREESCALE

176 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

7-8

Freescale Semiconductor

7.9 Register Descriptions (COP_BASE = $1FFFD0)

7.9.1 COP Control Register (COPCTL)

Figure 7-4. COP Control Register (COPCTL)

See Programmer’s Sheet on Appendix page B-18

7.9.1.1 Reserved—Bits 15–5

This bit field is reserved or not implemented. Each bit in the field is read as 0 and cannot be

modified by writing.

7.9.1.2 Bypass (BYPS)—Bit 4

This bit is intended for factory use only. Setting this bit allows testing time of the COP to be

accelerated by routing the IPBus clock to the counter instead of the OSCCLK. This bit should not

be set during normal operation of the chip. If this bit is used, however, it should only be changed

while the CEN bit is set to 0.

•

0 = Counter uses OSCCLK (default)

•

1 = Counter uses IPBus clock

7.9.1.3 COP Stop Mode Enable (CSEN)—Bit 3

This bit controls the operation of the COP counter in the Stop mode. This bit can only be changed

when the CWP bit is set to 0.

•

0 = COP counter will stop in the Stop mode (default)

•

1 = COP counter will run in the Stop mode if CEN is set to 1

7.9.1.4 COP Wait Mode Enable (CWEN)—Bit 2

This bit controls the operation of the COP counter in the Wait mode. This bit can only be changed

when the CWP bit is set to 0.

•

0 = COP counter will stop in the Wait mode (default)

•

1 = COP counter will run in the Wait mode if CEN is set to 1

Base + $0

Read

BYPS CSEN CWEN CEN

CWP

Write

Reset

000

DSP56857 датащи(PDF) 176 Page - Freescale Semiconductor, Inc