DSP56857 datasheet(177/662 Pages) FREESCALE

177 / 662 page

Power-On Reset (POR) and Computer Operating Properly (COP), Rev. 4

Freescale Semiconductor

7-9

7.9.1.5 COP Enable (CEN)—Bit 1

This bit controls the operation of the COP counter. This bit can only be changed when the CWP

bit is set to 0. This bit always reads as 0 when the chip is in the Debug mode.

•

0 = COP counter is disabled (default)

•

1 = COP counter is enabled

7.9.1.6 COP Write Protect (CWP)—Bit 0

This bit controls the write protection feature of the COP Control (COPCTL) register and the COP

Time-Out (COPTO) register. Once set, this bit can only be cleared by resetting the module.

•

0 = COPCTL and COPTO are readable and writable (default)

•

1 = COPCTL and COPTO are read only

7.9.2 COP Time-Out Register (COPTO)

Figure 7-5. COP Time-Out Register (COPTO)

See Programmer’s Sheet on Appendix page B-19

7.9.2.1 COP Time-Out Period (TIMEOUT)—Bits 15–0

The value in this register determines the time-out period of the COP counter. TIMEOUT should

be written before the COP is enabled. Once the COP is enabled, the recommended procedure for

changing TIMEOUT is to disable the COP, write to COPTO, then re-enable the COP, ensuring

the new TIMEOUT is loaded into the counter. Alternatively, the CPU can write to COPTO, then

write the proper patterns to COPCTR, causing the counter to reload with the new TIMEOUT

value. The COP counter is not reset by a write to COPTO. Changing TIMEOUT while the COP

is enabled will result in a time-out period differing from the expected value. These bits can only

be changed when the CWP bit is set to 0.

Base + $1

Read

TIMEOUT

Write

Reset

1111

11111

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