DSP56857 datasheet(174/662 Pages) FREESCALE

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Operating Modes

5685X Digital Signal Controller User Manual, Rev. 4

7-6

Freescale Semiconductor

7.5.3 COP After Reset

COPCTL is cleared out of reset. Thus the counter is disabled by default. In addition, COPTO is

set to it’s maximum value of $FFFF during reset so the counter is loaded with a maximum

time-out period when reset is released.

7.5.4 Wait Mode Operation

If both CEN and CWEN are set to 1 and the Wait mode is entered, the COP counter will continue

to count down. If either CEN or CWEN is set to 0 when Wait mode is entered, the counter will be

disabled and will reload using the value in the COPTO register.

7.5.5 Stop Mode Operation

If both CEN and CSEN set to 1 and the Stop mode is entered, the COP counter will continue to

count down. If either CEN or CSEN is set to 0 when Stop mode is entered, the counter will be

disabled and will reload using the value in the COPTO register.

7.5.6 Debug Mode Operation

The COP counter does not count when the chip is in the Debug mode. Additionally, the CEN bit

in the COPCTL always reads as 0 when the chip is in the Debug mode. The actual value of CEN

is unaffected by debug however, and it resumes it’s previously set value upon exiting Debug.

7.6 Operating Modes

The COP module design contains two major modes of operation:

•

Functional Mode

The COP by default is in this mode and will remain in this mode for as long as the

SCANTESTMODE input remains low.

•

Debug Mode

The COP timer is stopped while the processor is in Debug mode. If the COP is enabled,

the timer will resume, counting upon exiting Debug mode. The CEN bit in COPCTL

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