DSP56857 datasheet(182/662 Pages) FREESCALE

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Features

5685X Digital Signal Controller User Manual, Rev. 4

8-4

Freescale Semiconductor

The Vector Table is structured as two words per vector. This implies the Interrupt Vector offset,

added to the Vector Base Address, will be the vector number multiplied-by two. If the first

instruction of an interrupt vector is a JSR or BSR, the core assumes a standard long interrupt.

This is the normal case.

The core then saves the status register and program counter and vectors to the address pointed to

by the JSR. The interrupt is cleared by executing the return from interrupt instruction (RTI or

RTID) at the end of the interrupt service routine.

The interrupt controller can also support up to two fast interrupts. There are four programmable

registers in the controller, two for each fast interrupt, allowing set-up of a vector number to be

configured as a fast interrupt, and a 21-bit absolute vector address pointing to the interrupt

service routine.

When the Fast Interrupt Vector Number register is programmed, the interrupt controller will

intercept the normal vector table processing and insert the absolute address into the core via the

VAB bus. As long as the first instruction of the interrupt service routine is not a JSR or a BSR,

the core will interpret the interrupt as a fast interrupt and begin inserting the code into the

pipeline until a Fast Return from Interrupt (FRTID) is executed. The interrupt priority must be set

to level two for the fast interrupt to operate properly. Further, there can not be a JSR or BSR as

the first instruction of the fast interrupt service routine. The return from interrupt must use the

Fast Return from Interrupt (FRTID) instruction to clear the interrupt.

Reset is considered to be the highest priority interrupt and will take precedence over all other

interrupts. If the Reset pin is pulled low the interrupt controller will generate a reset vector

address for the core and assert the re-signal in the core.

8.2 Features

The ITCN module design includes these capabilities:

•

Programmable priority levels for each IRQ

•

Two programmable Fast Interrupts

•

Notification to SIM module to restart clocks out of Wait and Stop modes

8.3 Signal Description

The ITCN module interfaces with the IPBus, the 56800E core, and the IRQ sources. There are no

chip outputs driven directly by this module, but the IRQA and IRQB chip inputs do come to the

ITCN where they are re-synchronized to the system clock before use.

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