DSP56857 datasheet(173/662 Pages) FREESCALE

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Computer Operating Properly (COP) Module

Power-On Reset (POR) and Computer Operating Properly (COP), Rev. 4

Freescale Semiconductor

7-5

For the digital power supply the POR trip point is:

This means, as long as the analog power supply is below 2.8V, the POR_3p3 will be high. When

the analog power supply exceeds 2.9V the POR_3p3 output will be low. Respectively, for the

digital power supply, when the digital power supply is below 1.62V the POR_1p8 output will be

high. When the digital power supply is above 1.7V the POR_1p8 output will be low.

7.5 Computer Operating Properly (COP) Module

The Computer Operating Properly (COP) module is used to help software recover from runaway

code. The COP is a free-running down counter, once enabled is designed to generate a Reset

upon reaching zero. Software must periodically service the COP in order to clear the counter and

prevent a reset.

7.5.1 COP Functional Description

When the COP is enabled, each positive edge of OSCCLK will cause the counter to decrement by

one. If the count reaches a value of $0000, then the COP_RST signal is asserted and the chip is

reset. In order for the CPU to show it is operating properly, it must perform a service routine prior

to the count reaching $0000. The service routine consists of writing $5555 followed by $AAAA

to COPCTR.

7.5.2 Time-Out Specifications

The COP uses a 16-bit counter, being clocked by the crystal oscillator clock prescaled by 128.

Table 7-1 presents the range of time-out values supported as a function of oscillator frequency.

For a crystal operating at 4MHz the clock to the COP counter will be 31.25KHz. The value of the

COPTO register can be programmed from 1 to 65535 giving a time-out period range from 32µsec

minimum to 2.1sec maximum.

Absolute Minimum

Nominal

Absolute Maximum

1.62V

1.66V

1.7V

Table 7-1. COP Time-out Ranges as a Function of Oscillator Frequency

2 MHz

4MHz

$0000

64 µsec

32 µsec

$FFFF

4.2 sec

2.1 sec

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