DSP56857 datasheet(125/662 Pages) FREESCALE

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Resets

System Integration Module (SIM), Rev. 4

Freescale Semiconductor

4-17

The SIM has special control relationships with both the Oscillator (OSC) module and the Phase

Locked Loop (PLL) module. By default, the SIM provides an extreme low power Stop mode

(when OMR6_SD set to zero), by shutting down the PLL and, if possible, the oscillator output

amplifiers. Alternatively (when OMR6_SD set to one), the SIM supports a fast Stop mode

recovery and does not affect the state of the PLL or oscillator when the Stop mode is entered.

Extreme low power Stop mode works in this manner: upon entering the Stop mode, the SIM

asserts its PLL_SHUTDOWN output causing the PLL to be disabled and bypassed. One cycle

later, it asserts its OSC_LOPWR output. This feeds the LOW_PWR_MODE input of the OSC.

When the TOD clock prescaler in the OSC module is used (TOD_SEL bit in CGM Control

amplifiers for maximum power savings. When the CGM TOD clock prescaler is used

(TOD_SEL bit is one), OSC_LOPWR is ignored because the CGM depends on clocking from

OSC to generate the TOD clock.

When a fast Stop mode recovery is applied (the OMR6_SD bit in the core is set) neither

OSC_LOPWR nor PLL_SHUTDOWN will assert during the Stop mode entry. In this case, the

Stop mode entry leaves the clock generation system alone. When there is a return to the Run

mode, the clock (PLL based or direct), will be just as it was when Stop was entered, avoiding any

need to wait for PLL lock.

The SIM does not automatically restart and engage the PLL upon recovery from extreme Low

Power mode. This responsibility is left to the applications software. Refer to the documentation

of the Oscillator module for details on its Low Power mode input.

A final note on timing: Entry into either the Wait or Stop modes occurs at the next system clock

edge after p5STOP or p5WAIT asserts. Their disabling effect on clock generation will start one

clock cycle after that. The timing of entry into Low Power modes, especially the Stop mode, is

critical and is managed by a state machine in the Power Mode Control module. This module

ensures while in the Stop mode entry, PLL_SHUTDOWN asserts and the PLL is disabled and in

Bypass mode before OSC_LOPWR asserts possibly shutting off the clock input to the PLL.

4.10 Resets

The SIM supports four sources of reset. The two asynchronous sources are the external reset pin

and the Power-On Reset (POR). The two synchronous sources are the software reset, generated

within the SIM itself, and the COP reset. The reset generation module has two reset detectors. A

chip internal reset is detected when any of the sources assert. A POR reset is detected only when

the POR input asserts. The detectors remain asserted until the last active reset source deasserts.

The chip-internal reset detector output is the primary reset used within the SIM. The only

exception is the Software Control registers, reset by the POR reset detector and the Boot mode

field in the SIMCTL register, reset by the mode reset detector.

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