PC755 datasheet(47/50 Pages) ATMEL

47 / 50 page

PC755/745

2138D–HIREL–06/03

Alternately, the following is another method to determine the output impedance of the

PC755. A voltage source, V

force, is connected to the output of the PC755 as in Figure 33.

Data is held low, the voltage source is set to a value that is equal to (L2)OV

DD/2 and the

current sourced by V

force is measured. The voltage drop across the pull-down device,

which is equal to (L2)OV

DD/2, is divided by the measured current to determine the output

impedance of the pull-down device, R

N. Similarly, the impedance of the pull-up device is

determined by dividing the voltage drop of the pull-up, (L2)OV

DD/2, by the current sank

by the pull-up when the data is high and V

force is equal to (L2)OVDD/2. This method can

be employed with either empirical data from a test set up or with data from simulation

models, such as IBIS.

P and RN are designed to be close to each other in value. Then Z0 = (RP + RN)/2.

Figure 33 describes the alternate driver impedance measurement circuit.

Figure 33. Alternate Driver Impedance Measurement Circuit

Table 20 summarizes the signal impedance results. The driver impedance values were

characterized at 0

°C, 65°C, and 105°C. The impedance increases with junction temper-

ature and is relatively unaffected by bus voltage.

Pull–up Resistor

Requirements

The PC755 requires pull-up resistors (1 k

Ω – 5 kΩ) on several control pins of the bus

interface to maintain the control signals in the negated state after they have been

actively negated and released by the processor or other bus masters. These pins are

TS, ABB, AACK, ARTRY, DBB, DBWO, TA, TEA, and DBDIS. DRTRY should also be

connected to a pull-up resistor (1 k

Ω – 5 kΩ) if it will be used by the system; otherwise,

this signal should be connected to HRESET to select NO-DRTRY mode.

Three test pins also require pull-up resistors (100

Ω – 1 kΩ). These pins are

L1_TSTCLK, L2_TSTCLK, and LSSD_MODE. These signals are for factory use only

and must be pulled up to OV

DD for normal machine operation.

Table 20. Impedance Characteristics

DD = 2.0V, OVDD = 3.3V, T

c = 0 - 105°C

Impedance

Processor bus

L2 bus

Symbol

Unit

25-36

26-39

(L2)OVDD

BGA

Data

OGND

Vforce

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