PC755 datasheet(30/50 Pages) ATMEL

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PC755/745

2138D–HIREL–06/03

The L2CLK_OUT timing diagram is shown in Figure 14.

Figure 14. L2CLK_OUT Output Timing Diagram

L2 Bus Input AC Specifications

Table 16 provides the L2 bus interface AC timing specifications for the PC755 as

defined in Figure 15 and Figure 16 for the loading conditions described in Figure 17.

VM = Midpoint Voltage (L2OVdd/2)

L2CLK_OUTA

L2CLK_OUTB

L2 Differential Clock Mode

L2 Single-Ended Clock Mode

L2SYNC_OUT

L2CLK_OUTA

tL2CR

tL2CF

L2CLK_OUTB

L2SYNC_OUT

tL2CSKW

tL2CLK

tCHCL

Table 16. L2 Bus Interface AC Timing Specifications at Recommended Operating Conditions

Parameter

Symbol

All Speed Grades

Unit

Min

Max

L2SYNC_IN rise and Fall Time(1)

L2CR & tL2CF

–

1.0

Setup Times: Data and Parity(2)

DVL2CH

1.2

Input Hold Times: Data and Parity(2)

DXL2CH

Valid Times: (3)(4)

All Outputs when L2CR[14-15] = 00

All Outputs when L2CR[14-15] = 01

All Outputs when L2CR[14-15] = 10

All Outputs when L2CR[14-15] = 11

L2CHOV

3.1

3.2

3.3

3.7

Output Hold Times: (3)

All Outputs when L2CR[14-15] = 00

All Outputs when L2CR[14-15] = 01

All Outputs when L2CR[14-15] = 10

All Outputs when L2CR[14-15] = 11

L2CHOX

0.5

0.7

0.9

1.1

L2SYNC_IN to High Impedance:(3)(5)

All Outputs when L2CR[14-15] = 00

All Outputs when L2CR[14-15] = 01

All Outputs when L2CR[14-15] = 10

All Outputs when L2CR[14-15] = 11

L2CHOZ

2.4

2.6

2.8

3.0

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