31

PC755/745

2138D–HIREL–06/03

Notes:

2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.

3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-

nal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50

Ω load (See

Figure 10).

4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous Bur-

stRAMs, L2CR[14

recommended.

5. Guaranteed by design and characterization.

6. Revisions prior to Rev 2.8 (Rev E) were limited in performance.and did not conform to this specification. Contact your local

Atmel sales office for more information.

Figure 15 shows the L2 bus input timing diagrams for the PC755.

Figure 15. L2 Bus Input Timing Diagrams

Figure 16 shows the L2 bus output timing diagrams for the PC755.

Figure 16. L2 Bus Output Timing Diagrams

Figure 17 provides the AC test load for L2 interface of the PC755.

Figure 17. AC Test Load for the L2 Interface

L2SYNC_IN

L2 DATA AND DATA

VM

VM = Midpoint Voltage (L2OVDD/2)

PARITY INPUTS

L2SYNC_IN

ALL OUTPUTS

VM

VM = Midpoint Voltage (L2OVDD/2)

VM

L2DATA BUS

tL2CHOX

tL2CHOZ

tL2CHOV

OUTPUT

L2OVdd/2