PC755 datasheet(22/50 Pages) ATMEL

22 / 50 page

PC755/745

2138D–HIREL–06/03

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances

are a common figure-of-merit used for comparing the thermal performance of various

microelectronic packaging technologies, one should exercise caution when only using

this metric in determining thermal management because no single parameter can ade-

quately describe three-dimensional heat flow. The final die-junction operating

temperature, is not only a function of the component-level thermal resistance, but the

system-level design and its operating conditions. In addition to the component’s power

consumption, a number of factors affect the final operating die-junction temperature —

airflow, board population (local heat flux of adjacent components), heat sink efficiency,

heat sink attach, heat sink placement, next-level interconnect technology, system air

temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for

today’s microelectronic equipment, the combined effects of the heat transfer mecha-

nisms (radiation, convection and conduction) may vary widely. For these reasons, we

recommend using conjugate heat transfer models for the board, as well as, system-level

designs. To expedite system-level thermal analysis, several “compact” thermal-package

models are available within FLOTHERM

®. These are available upon request.

Power consideration

Power management

The PC755 provides four power modes, selectable by setting the appropriate control

bits in the MSR and HIDO registers. The four power modes are as follows:

•

Full-power: This is the default power state of the PC755. The PC755 is fully

powered and the internal functional units operate at the full processor clock speed.

If the dynamic power management mode is enabled, functional units that are idle

will automatically enter a low-power state without affecting performance, software

execution, or external hardware.

•

Doze: All the functional units of the PC755 are disabled except for the time

base/decrementer registers and the bus snooping logic. When the processor is in

doze mode, an external asynchronous interrupt, a system management interrupt, a

decrementer exception, a hard or soft reset, or machine check brings the PC755

into the full-power state. The PC755 in doze mode maintains the PLL in a fully

powered state and locked to the system external clock input (SYSCLK) so a

transition to the full-power state takes only a few processor clock cycles.

•

Nap: The nap mode further reduces power consumption by disabling bus snooping,

leaving only the time base register and the PLL in a powered state. The PC755

returns to the full-power state upon receipt of an external asynchronous interrupt, a

system management interrupt, a decrementer exception, a hard or soft reset, or a

machine check input (MCP). A return to full-power state from a nap state takes only

a few processor clock cycles. When the processor is in nap mode, if QACK is

negated, the processor is put in doze mode to support snooping.

•

Sleep: Sleep mode minimizes power consumption by disabling all internal functional

units, after which external system logic may disable the PPL and SUSCLK.

Returning the PC755 to the full-power state requires the enabling of the PPL and

SYSCLK, followed by the assertion of an external asynchronous interrupt, a system

management interrupt, a hard or soft reset, or a machine check input (MCP) signal

after the time required to relock the PPL.

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