PC755 datasheet(44/50 Pages) ATMEL

44 / 50 page

PC755/745

2138D–HIREL–06/03

The PC755 generates the clock for the external L2 synchronous data SRAMs by divid-

ing the core clock frequency of the PC755. The divided-down clock is then phase-

adjusted by an on-chip delay-lock-loop (DLL) circuit and should be routed from the

PC755 to the external RAMs. A separate clock output, L2SYNC_OUT is sent out half

the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN

so that the rising-edge of the clock as seen at the external RAMs can be aligned to the

clocking of the internal latches in the L2 bus interface.

The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of

the L2CR register. Generally, the divisor must be chosen according to the frequency

supported by the external RAMs, the frequency of the PC755 core, and the phase

adjustment range that the L2 DLL supports. Figure 18 shows various example L2 clock

frequencies that can be obtained for a given set of core frequencies. The minimum L2

frequency target is 80 MHz.

Note:

The core and L2 frequencies are for reference only. Some examples may repre-

sent core or L2 frequencies which are not useful, not supported, or not tested

for by the PC755; see Section “L2 Clock AC Specifications” page 28 for valid

L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies

less than 110 MHz.

System Design

Information

PLL Power Supply Filtering

The AV

DD and L2AVDD power signals are provided on the PC755 to provide power to the

clock generation phase-locked loop and L2 cache delay-locked loop respectively. To

ensure stability of the internal clock, the power supplied to the AV

DD input signal should

be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL.

A circuit similar to the one shown in Figure 31 using surface mount capacitors with mini-

mum Effective Series Inductance (ESL) is recommended. Consistent with the

recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of

Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recom-

mended over a single large value capacitor.

Table 19. Sample Core-to-L2 Frequencies

Core Frequency in MHz

1.5

2.5

250

166

125

100

266

177

133

106

275

183

138

110

300

200

150

120

100

325

217

163

130

108

333

222

167

133

111

350

233

175

140

117

366

244

183

146

122

375

250

188

150

125

400

266

200

160

133

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