25

PC755/745

2138D–HIREL–06/03

Clock AC Specifications

Table 12 provides the clock AC timing specifications as defined in Table 3.

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0

quency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0

2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for selectable I/O bus

interface levels. The minimum slew rate of 1v/ns is equivalent to a 2ns maximum rise/fall time measured at 0.4V and 2.4V or

a rise/fall time of 1ns measured at 0.4V to 1.4V.

3. Timing is guaranteed by design and characterization.

4. This represents total input jitter – short term and long term combined and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization. PLL

PLL lock after a stable V

when the PLL has been disabled and subsequently re

asserted for a minimum of 255 bus clocks after the PLL

Figure 10 provides the SYSCLK input timing diagram.

Figure 10. SYSCLK Input Timing Diagram

Table 12. Clock AC Timing Specifications at Recommended Operating Conditions (See Table 5)

Characteristic

Symbol

Maximum Processor Core Frequency

Unit

300 MHz

350 MHz

400 MHz

Min

Max

Min

Max

Min

Max

Processor frequency(1)

200

300

200

350

200

400

MHz

VCO frequency(1)

400

600

400

700

400

800

MHz

SYSCLK frequency(1)

f

SYSCLK

25

100

25

100

25

100

MHz

SYSCLK cycle time

10

40

10

40

10

40

ns

SYSCLK rise and fall time(2)

–

2

–

2

–

2

ns

t

–

1.4

–

1.4

–

1.4

ns

(3)

40

60

40

60

40

60

%

SYSCLK jitter(3)(4)

–

150

–

150

–

150

ps

Internal PLL relock time(3)(5)

–

100

–

100

–

100

µs

SYSCLK

VM

VM

VM

KVIH

KVIL

VM = Midpoint Voltage (OVDD/2)