26

PC755/745

2138D–HIREL–06/03

Processor Bus AC

Specifications

Table 13 provides the processor bus AC timing specifications for the PC755 as defined

in Figure 11 and Figure 13. Timing specifications for the L2 bus are provided in Section

“L2 Clock AC Specifications» page 28.

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-

nal in question. All output timings assume a purely resistive 50

Ω load (See Figure 11). Input and output timings are

measured at the pin; time

to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

going highs) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal

(I) went invalid (X) with respect to the rising clock edge (KH)

output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). For additional explana-

tion of AC timing specifications in Motorola PowerPC microprocessors, see the application note “Understanding AC Timing

Specifications for PowerPC Microprocessors.”

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 11).

4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of

255 bus clocks after the PLL re

5. t

by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.

6. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0

7. Guaranteed by design and characterization.

8. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during operation

will cause the bus mode voltage selection to change. Changing the logic states of the PLL_CFG pins during operation will

cause the PLL division ratio selection to change. Both of these conditions are considered outside the specification and are

not supported. Once HRESET is negated the states of the bus mode selection pins must remain stable.

Figure 11 provides the mode select input timing diagram for the PC755.

Figure 11. Mode Input Timing Diagram

Table 13. Processor Bus Mode Selection AC Timing Specifications(1)

Parameter

Symbols(2)

All Speed Grades

Unit

Min

Max

Mode select input setup to HRESET(3)(4)(5)(6)(7)

8

–

HRESET to mode select input hold(3)(4)(6)(7)(8)

t

MXRH

0

–

ns

HRESET

MODE SIGNALS

VM = Midpoint Voltage (OVDD/2)

VM

tMVRH

tMXRH