PC755 datasheet(28/50 Pages) ATMEL

28 / 50 page

PC755/745

2138D–HIREL–06/03

Figure 13 provides the input/output timing diagram for the PC755.

Figure 13. Input/Output Timing Diagram

L2 Clock AC Specifications

The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4:6])

core-to-L2 divisor ratio. See Table 15 for example core and L2 frequencies at various

divisors. Table 15 provides the potential range of L2CLK output AC timing specifications

as defined in Figure 14.

The minimum L2CLK frequency of Table 15 is specified by the maximum delay of the

internal DLL. The variable-tap DLL introduces up to a full clock period delay in the

L2CLKOUTA, L2CLKOUTB, and L2SYNC_OUT signals so that the returning

L2SYNC_IN signal is phase aligned with the next core clock (divided by the L2 divisor

ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this

minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase

aligned with the PC755 core clock at the SRAMs.

The maximum L2CLK frequency shown in Table 15 is the core frequency divided by

one. Very few L2 SRAM designs will be able to operate in this mode. Most designs will

select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write

access to the L2 SRAMs. The maximum L2CLK frequency for any application of the

PC755 will be a function of the AC timings of the PC755, the AC timings for the SRAM,

bus loading, and printed circuit board trace length.

SYSCLK

ALL INPUTS

VM = Midpoint Voltage (OVDD/2 or Vin/2)

ALL OUTPUTS

(Except TS, ABB,

ARTRY, DBB)

TS,ABB,DBB

ARTRY

tIVKH

tIXKH

tKHOE

tKHOV

tKHOX

tKHABPZ

tKHOV

tKHOX

tKHOZ

tKHARPZ

tKHOV

tKHOX

tKHARP

tKHOV

tKHOZ

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