PC755 datasheet(43/50 Pages) ATMEL

43 / 50 page

PC755/745

2138D–HIREL–06/03

Notes:

1. PLL_CFG[0:3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC755; see Section «Clock AC Specifications»

page 25 for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode

is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL off mode, no clocking occurs inside the PC755 regardless of the SYSCLK input.

Table 18. PC755 Microprocessor PLL Configuration

PLL_CFG [0-3]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-Core

Multiplier

Core-to VCO

Multiplier

Bus 33

MHz

Bus 50

MHz

Bus 66

MHz

Bus 75

MHz

Bus 80

MHz

Bus 100

MHz

0100

200

(400)

1000

200

(400)

225

(450)

240

(480)

300

(600)

1110

3.5x

233

(466)

263

(525)

280

(560)

350

(700)

1010

200

(400)

266

(533)

300

(600)

320

(640)

400

(800)

0111

4.5x

225

(450)

300

(600)

338

(675)

360

(720)

1011

250

(500)

333

(666)

375

(750)

400

(800)

1001

5.5x

275

(550)

366

5733

1101

200

(400)

300

(600)

400

(800)

0101

6.5x

216

(433)

325

(650)

0010

233

(466)

350

(700)

0001

7.5x

250

(500)

375

(750)

1100

266

(533)

400

(800)

0110

10x

333

(666)

0011

PLL off/bypass

PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

1111

PLL off

PLL off, no core clocking occurs

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