PC87372 datasheet(108/144 Pages) NSC

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8.0 Glue Functions (Continued)

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Revision 1.2

8.2.8

CNR Downstream Codec Dynamic Control

This function generates the CDC_DWN_RST signal, which enables the audio CNR board.

An active low codec reset signal (CDC_DWN_RST) is generated either when an active (low) AUD_LINK_RST is received

or when CNR Downstream Codec is disabled (CDC_DWN_ENAB = high).

The level of the CDC_DWN_ENAB system configuration signal is controlled as follows:

Externally, by connecting a pull-down resistor between the CDC_DWN_ENAB pin and GND (in this case, the output

buffer of GPIO14 must be disabled; see Section 3.13.4 on page 57)

Internally, by enabling the output buffer of GPIO14 and by writing the required level for CDC_DWN_ENAB to bit 4 of

GPDO1 (or GPDIO1) register; see Section 5.4.3 on page 68 (in this case, it is not necessary to remove the pull-down

resistor if it is connected between the CDC_DWN_ENAB pin and GND).

Figure 28 shows a simplified diagram of the circuit that generates the CDC_DWN_RST signal.

Figure 28. CDC_DWN_RST Generation (Simpliﬁed Diagram)

For the AC characteristics, see CNR Downstream Codec Dynamic Control on page 142.

8.2.9

Hard-Disk LED Indicator Control

This function generates the HD_LED signal, which controls the Hard Drive, red LED indicator.

The Hard Drive LED is turned on by an active low HD_LED signal, generated when at least one of the PRIMARY_HD or

SECONDARY_HD or SCSI pins is active (low).

Figure 29 shows a simplified diagram of the circuit that generates the HD_LED signal.

Figure 29. HD_LED Generation (Simpliﬁed Diagram)

8.2.10 SMBus Voltage Translation

This function performs “passive” level translation between the VDD3-powered 3V_DDCSCL and 3V_DDCSDA signals and

the VDD5-powered 5V_DDCSCL and 5V_DDCSDA signals, respectively, for interfacing the Data Display Channel.

The signals connected to the 3V_DDCSCL, 3V_DDCSDA, 5V_DDCSCL and 5V_DDCSDA pins are compatible with Intel's

SMBus (Speciﬁcation Rev 1.1, Dec. 11, 1998) two-wire synchronous serial interface speciﬁcations.

10 K

Ω

Buffer

CDC_DWN_RST

CDC_DWN_ENAB

AUD_LINK_RST

GPIO14

Input

Buffer

Output

220

Ω

HD_LED

VDD3

SCSI

PRIMARY_HD

LED

SECONDARY_HD

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