PC87372 datasheet(62/144 Pages) NSC

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Revision 1.2

4.0

LPC Bus Interface

With the exception of the Glue Functions, the host can access all the functional blocks of the PC87372 device through the

LPC bus.

4.1 OVERVIEW

The LPC host interface supports 8-bit I/O Read, 8-bit I/O Write and 8-bit DMA transactions, as defined in Intel’s LPC Interface

Speciﬁcation, Revision 1.0.

4.2 LPC TRANSACTIONS

The LPC interface of the PC87372 device responds to the following LPC transactions:

• 8-bit I/O read and write cycles

• 8-bit DMA read and write cycles

• DMA request cycles

4.3 LPCPD FUNCTIONALITY

The PC87372 device supports LPCPD functionality. LPCPD is used when the VDD3 power supply is not shared by all the

devices connected to the LPC bus. The LPCPD signal conforms with Intel’s LPC Interface Specification, Revision 1.00. Note

that if the PC87372 power supply is on while LPCPD is active (indicating the LPC bus is powered down), the PC87372 does

not have to be reset when LPCPD is de-asserted (indicating that power is returned to the LPC bus).

When the LPCPD functionality is not required, the LPCPD pin must be left unconnected. Connecting the LPCPD pin to the

VDD3 power supply is not recommended.

4.4 INTERRUPT SERIALIZER

The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from internal IRQ sources into serial in-

terrupt request data transmitted over the SERIRQ bus. This enables devices that support only parallel IRQs to be integrated

into a system that supports only serial IRQs like the LPC bus.

Each internal IRQ is fed into a Mapping, Enable and Polarity Control block, which maps the IRQ to its associated IRQ num-

bers (see Table 12 on page 33). The resulting IRQs are then fed into the Interrupt Serializer, where they are translated into

serial data and then transmitted over the SERIRQ bus. Each interrupt number is assigned a time slot in the SERIRQ frame.

Different IRQ sources in the PC87372 device cannot share the same interrupt number and thus cannot share the same time

slot in the SERIRQ frame.

When a transition is detected on an IRQ source, the new value of the IRQ source is transmitted over the SERIRQ bus during

the corresponding IRQ slot. For example, when a transition on the Serial Port IRQ is detected, the new value of the Serial

Port IRQ is transmitted during time slot n of the SERIRQ bus.

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