PC87372 datasheet(55/144 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision 1.2

3.13 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION

3.13.1 General Description

The GPIO functional block includes 13 pins arranged in two ports:

Port 0 contains eight GPIOE pins (i.e., GPIO pins with event detection).

Port 1 contains four GPIOE pins and one GPIO pin.

The pins of Ports 0 and 1 have full event detection capability (see Section 1.3 on page 13), enabling them to trigger an IRQ.

In addition, through the SWC functional block, the pins of Ports 0 and 1 can trigger the SIOPME signal. An exception is the

GPIO14 pin of Port 1, which has no event detection and therefore cannot trigger IRQ or SIOPME.

All 13 GPIO pins are powered from the VSB3 well. The 10 runtime registers associated with the two ports are arranged in

the GPIO address space as shown in Table 22. Each GPIO port with wake-up event detection capability has five runtime

registers. The GPIO base address is 32-byte aligned. Address bits 4-0 are used to indicate the register offset.

The specific runtime registers implemented in the PC87372 devices are shown in Table 22. All of these registers are VSB3

powered.

Table 22. Runtime Registers in GPIO Address Space

Offset

Mnemonic

Port

Power Well

Type

SEPDIO1 =1

1. See Section 3.13.7 on page 59

SEPDIO = 0

00h

GPDO0

GPIO Data Out 0

VSB3

R/W

01h

GPDI0

GPIO Data In 0

VSB3

02h

GPEVEN0 GPIO Event Enable 0

VSB3

R/W

03h

GPEVST0 GPIO Event Status 0

VSB3

R/W1C

04h

GPDO1

GPIO Data Out 1

VSB3

R/W

05h

GPDI1

GPIO Data In 1

VSB3

06h

GPEVEN1 GPIO Event Enable 1

VSB3

R/W

07h

GPEVST1 GPIO Event Status 1

VSB3

R/W1C

15h

GPDIO0

GPIO Data In/Out 0

VSB3

R/W

16h

GPDIO1

GPIO Data In/Out 1

VSB3

R/W

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