PC87372 datasheet(52/144 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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3.11 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION

3.11.1 General Description

System Wake-Up Control provides wake-up and power management functionality according to the ACPI specification (see

Section 6.1 on page 70). Its registers are VSB3 powered.

3.11.2 Logical Device 4 (SWC) Configuration

Table 19 lists the configuration registers that affect the SWC. See Section 3.2.3 on page 32 for a detailed description of

these registers. All these registers are VDD3 powered.

Table 19. System Wake-Up Control (SWC) Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Power Well

Reset

30h

Activate. When bit 0 is cleared, the runtime registers of this logical device are

not accessible (see Section 3.3.1 on page 36).1

1. The logical device runtime registers are maintained and all wake-up detection mechanisms are functional.

R/W

VDD3

00h

60h

SWC Base Address MSB register

R/W

VDD3

00h

61h

SWC Base Address LSB register. Bits 3-0 (for A3-0) are read only, ‘0000’.

R/W

VDD3

00h

62h

GPE1_BLK Base Address MSB register

R/W

VDD3

00h

63h

GPE1_BLK Base Address LSB register. Bits 3-0 (for A3-0) are read only, ‘0000’.

R/W

VDD3

00h

70h

Interrupt Number

R/W

VDD3

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only

R/W

VDD3

03h

74h

Report no DMA assignment

VDD3

04h

75h

Report no DMA assignment

VDD3

04h

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