PC87372 datasheet(22/144 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

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Revision 1.2

1.4.12 Power and Ground

1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS

The signals listed in Table 3 have internal pull-up (PU) and/or pull-down (PD) resistors. The internal resistors are optional

for those signals indicated as “Programmable”. See Section 10.3 on page 127 for the values of each resistor type.

XOR_OUT

O3/6

VDD3

XOR Tree Output. All the device pins (except power type and

analog type pins) are internally connected in a XOR tree

structure.

1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recom-

mended for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 K

Ω. If, how-

ever, a TTL transceiver device is used, the value of the external pull-down resistor must be 470

Ω, and since the

Serial Port pins are not able to drive this load, the external pull-down resistor must be disconnected tEPLV after

VDD3 power-up (see “VDD Power-Up Reset” on page 130).

Signal

Pin(s)

I/O Buffer Type

Power

Well

Description

VSS

8, 29, 46, 58,

78, 96, 110

GND

Ground. Ground connection for both core logic and I/O buffers,

for the Main and Standby power supplies.

VDD3

6, 31, 49, 60

PWR

Main 3.3V Power Supply. Powers the I/O buffers of the legacy

peripherals and the LPC interface.

VSB3

76, 93, 107

PWR

Standby 3.3V Power Supply. Powers the I/O buffers of the

GPIO ports, SWC, Glue Functions and the on-chip Core power

converter.

VCORF

I/O

PWR

On-chip Core Power Converter Filter. On-chip Core power

converter output. Powers the core logic of all the device

modules. An external 1

µF ceramic filter capacitor must be

connected between this pin and VSS.

Table 3. Internal Pull-Up and Pull-Down Resistors

Signal

Pin(s)

Power Well

Type

Comments

LPC Interface

LPCPD

VDD3

PU30

Parallel Port

ACK

VDD3

PU220

AFD_DSTRB

VDD3

PU440

BUSY_WAIT

VDD3

PD120

ERR

VDD3

PU220

INIT

VDD3

PU440

VDD3

PU220/

PD120

Programmable

SLCT

VDD3

PD120

SLIN_ASTRB

VDD3

PU440

STB_WRITE

VDD3

PU440

Signal

Pin(s)

I/O Buffer Type Power Well

Description

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