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PC87372 датащи(PDF) 79 Page - National Semiconductor (TI) |
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PC87372 датащи(HTML) 79 Page - National Semiconductor (TI) |
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79 / 144 page ![]() 6.0 System Wake-Up Control (SWC) (Continued) 79 www.national.com Revision 1.2 6.3.3 SWC Miscellaneous Control Register (SWC_CTL) This register contains control and status bits for the SWC module. It is reset to 01h. Power Well: VSB3 Location: Offset 01h Type: Varies per bit Bit 76 5 43210 Name LOCKSCF Reserved LED_OPT Reset 0 0 0 00001 Bit Type Description 7 R/W1S LOCKSCF (Lock SWC Configuration). When set to 1, this bit locks the BLINK and GRN_YLW bits in SLEDCTL register, and all bits of SWC_CTL, ALEDCTL, LEDBLNK, KBDWKCTL, PS2CTL and PS2KEY0 −7 registers by disabling writing to them (including to the LOCKSCF bit itself). Once set, this bit can be cleared by VDD3 Power-Up reset (or Hardware reset). 0: R/W bits are enabled for write (default) 1: All bits are RO 6-1 Reserved. 0 R/W or RO LED_OPT (LED Control Option Select). Selects either the Standard or the Advanced LED control option for the two power LEDs. 0: Advanced: LEDs controlled by the ALEDCTL and LEDBLNK registers at offsets 02h and 03h, respec- tively 1: Standard: LEDs controlled by the SLEDCTL register at offset 00h (default) |
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