PC87372 datasheet(28/144 Pages) NSC

28 / 144 page

2.0 Power, Reset and Clocks (Continued)

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Revision 1.2

2.3.2

48 MHz Domain

The 48 MHz clock domain is sourced by the on-chip Clock Generator (supplied by the Main power plane).

Following a VDD Power-Up reset, the software waits a period of t14MW +t14MVAL until a valid 14.31818 MHz clock signal is

available at the CLOCKI14 pin. Then, the software can set the HFCGEN bit in the CLOCKCF register to 1. This bit enables

the operation of the Clock Generator.

After the Clock Generator is enabled for operation, its output clock is frozen to a low level until the generator provides an

internal clock signal that meets all requirements. When the requirements are met, the 48 MHz clock domain starts toggling.

The status of the Clock Generator output clock is indicated by CKVALID bit in CLOCKCF register. While the Clock Generator

is stabilizing, this bit is 0, indicating a 48 MHz clock domain frozen at low level. After t48MD, the 48 MHz clock domain starts

toggling and this bit is set to 1. The software must wait for CKVALID bit to be set before it enables the FSM or the Legacy

functions (Serial Port, Parallel Port, FDC, KBC).

The on-chip Clock Generator multiplies the frequency of the clock signal (received through the CLOCKI14 pin) by a constant

value to obtain the 48 MHz output frequency.

Figure 3 shows a simplified diagram of the 32 KHz and the 48 MHz clock domains.

Figure 3. 32 KHz and 48 MHz Clock Domains (Simpliﬁed Diagram)

2.3.3

32 KHz Domain

The 32 KHz clock domain, and the modules using it, are supplied by the Standby and Core power planes. Therefore, this

clock domain is active whenever the VSB3 and VCORF power supplies are on.

The 32 KHz clock domain is sourced by the CLOCKI32 pin. The clock signal from the CLOCKI32 pin passes through a Clock

Filter. The 32 KHz clock domain signal is held low by the 32KVAL output of the Clock Filter until a valid 32.768 KHz clock is

available at the CLOCKI32 pin. The 32 KHz clock domain signal starts toggling t32KW +t32KVAL after VSB3 Power-Up (Low-

Frequency Clock Timing on page 132).

2.4 TESTABILITY SUPPORT

The PC87372 device supports two testing techniques:

• In-Circuit Testing (ICT)

• XOR Tree Testing

2.4.1

ICT

The In-Circuit Testing (ICT) technique, also known as “bed-of-nails”, injects logic patterns to the input pins of the devices

mounted on the tested board. It then checks their outputs for the correct logic levels.

The PC87372 supports this testing technique by floating (putting in TRI-STATE) all the device pins. This prevents “back-

driving” the PC87372 pins by the ICT tester when a device normally controlled by PC87372 is tested (device inputs are driven

by the ICT tester).

To enter TRI-STATE mode, the TRIS pin must be pulled low (by a 10 K

Ω resistor to V

SS), and the TEST pin must be left

unconnected after both VDD3 and VSB3 power supplies are turned on. In addition, the PCI_RESET pin must be held low for

at least 10 ms (see VSB Power-Up Reset on page 129 and VDD Power-Up Reset on page 130). After PCI_RESET is de-

asserted, all the device output and I/O pins are floated (put in TRI-STATE); exceptions to this are the power supply pins

(VDD3,VSB3,VSS,VCORF), analog pins (VSB5, REF5V, REF5V_STBY), RSMRST and all “not connected” (N.C.) pins, which

do not float in TRI-STATE mode.

Clock

Generator

14.31818 MHz

CLOCKI14

Functions

Internal

48 MHz

CKVALID

(VDD3)

CLOCKI32

Functions

Internal

Filter

Clock

32.768 KHz

32KVAL

32 KHz Domain

48 MHz Domain

HFCGEN

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