PC87372 datasheet(106/144 Pages) NSC

106 / 144 page

8.0 Glue Functions (Continued)

106

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Revision 1.2

Table 40 defines the DC characteristics of the Resume Reset circuit. For the AC characteristics, see Resume Reset on page

140.

8.2.4

Main Power Good

This function generates the PWRGD_3V signal, indicating that the Main power supply voltage is valid and the reset button

on the front panel is not pressed. The PWRGD_3V signal indicates to system components that their input power supplies

are valid.

The FPRST input is debounced for at least tDB before entering the Main Power Good circuit, to ensure that the signal is

stable. The debouncer adds a tDB delay to the PWRGD_3V output change in output caused by the FPRST input. The de-

bouncer timing is based on the 32 KHz clock domain, which therefore must be valid to enable the correct operation of the

Power Good function.

The PWRGD_3V is the AND function of the PWRGD_PS and FPRST inputs. Figure 24 shows a simplified diagram of the

circuit that generates the PWRGD_3V signal.

Figure 24. PWRGD_3V Generation (Simpliﬁed Diagram)

For the AC characteristics, see Main Power Good on page 141.

8.2.5

Rambus SCK Clock Gate Control

This function generates the SCK_BJT_GATE signal, which controls an external circuit that gates the SCK clock to the Ram-

bus socket.

The SCK clock to the Rambus socket is disabled by an active high SCK_BJT_GATE signal, generated when either the Main

power supply voltage is not valid or the reset button on the front panel is pressed (PWRGD_3V = low).

Figure 25 shows a simplified diagram of the circuit that generates the SCK_BJT_GATE signal.

Figure 25. SCK_BJT_GATE Generation (Simpliﬁed Diagram)

For the AC characteristics, see CNR Downstream Codec Dynamic Control on page 142.

Table 40. Resume Reset Circuit DC Characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

VTRIP

VSB5 Threshold Level

VSB3 = 3.3V ±10%

4.2

4.5

ZOFF

Output Impedance at VSB3 Off

1. Not tested. Guaranteed by characterization.

VSB3 = 0V,

VSB5 =5V ±10%

710

Ω

FPRST

Input

Debouncer

PWRGD_PS

PWRGD_3V

1 K

Ω

SCK_BJT_GATE

VSB5

PWRGD_3V

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