PC87372 datasheet(27/144 Pages) NSC

27 / 144 page

2.0 Power, Reset and Clocks (Continued)

www.national.com

Revision 1.2

2.2.2

VDD Power-Up Reset

VDD Power-Up reset is generated by an internal circuit when VDD3 power is turned on. VDD Power-Up reset time (tIRST) lasts

until the PCI_RESET signal is de-asserted. The Hardware reset (PCI_RESET) must be asserted for a minimum of 10 ms to

ensure that the PC87372 device operates correctly.

External devices must wait at least tIRST before accessing the PC87372. If the host processor accesses the PC87372 during

this time, the PC87372 LPC interface ignores the transaction (that is, it does not return a SYNC handshake).

VDD Power-Up reset performs the following actions:

• Puts pins with strap options into TRI-STATE and enables their internal pull-up resistors

• Samples the logic levels of the strap pins

• Executes all the actions performed by the Hardware reset (see Section 2.2.3)

2.2.3

Hardware Reset

Hardware reset is activated by the assertion (low) of the PCI_RESET input while VDD3 is “good”. When VDD3 power is off,

the PC87372 device ignores the level of the PCI_RESET input. However, the PCIRST_OUT and PCIRST_OUT2 outputs

reflect the PCI_RESET input and thus are active (low). In addition, the Hardware reset (PCI_RESET) must be asserted after

VSB power-up, as described in Section 2.2.1.

Hardware reset performs the following actions:

• Resets all lock bits in configuration registers and SWC

• Sets up the pull-up option and the default source for the V

DD3-powered multiplexed output pins

• Executes all the actions performed by the Software reset (see Section 2.2.4)

2.2.4

Software Reset

The Software reset is triggered by the host setting SWRST bit in SIOCF1 register (see Section 3.7.2 on page 40) via the

LPC interface. The Host Software reset performs the following actions:

• Loads default values to the V

DD3-powered unlocked bits in the Configuration Control.

• Loads default values to the V

SB3-powered unlocked GPIO Configuration and Data bits for those GPIO ports with

VDDLOAD = 1. VDDLOAD bit is not affected.

• Resets all the V

DD3-powered Legacy logical devices.

• Loads default values to all the V

DD3-powered Legacy module registers.

2.3 CLOCK DOMAINS

The PC87372 device has three clock domains, as shown in Table 6.

The LPC and 48 MHz clock domains, and the modules using them, are supplied by the Main power plane. Therefore, these

two clock domains are active only when the VDD3 power supply is on.

2.3.1

LPC Domain

The LPC clock signal at the PCI_CLK pin must become valid (to the extent specified in PCI_CLK and PCI_RESET on page

133) before the end of the VDD Power-Up reset (see Section 2.2.2).

Table 6. Clock Domains of the PC87372

Clock

Domain

Frequency

Power

Plane

Source

Usage

LPC

Up to 33 MHz

VDD3

LPC clock input (PCI_CLK)

LPC bus Interface and Conﬁguration Registers

48 MHz

VDD3

On-chip Clock Generator

Legacy functions (Serial Port, Parallel Port,

FDC, KBC) and FSM

32 KHz

32.768 KHz

VSB3

Clock input (CLOCKI32)

SWC, GPIO and Glue Functions

PC87372 датащи(PDF) 27 Page - National Semiconductor (TI)

PC87372 датащи(HTML) 27 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL