PC87372 datasheet(69/144 Pages) NSC

69 / 144 page

5.0 General-Purpose Input/Output (GPIO) Ports (Continued)

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Revision 1.2

5.4.5

GPIO Event Enable Register (GPEVEN)

Power Well: VSB3

Location:

Device specific

Type:

R/W or RO

5.4.6

GPIO Event Status Register (GPEVST)

Power Well: VSB3

Location:

Device specific

Type:

R/W1C or RO

5.4.7

GPIO Data In/Out Register (GPDIO)

Power Well: VSB3

Location:

Device specific

Type:

R/W

Bit

76543210

Name

EVTENA

Reset

00000000

Bit

Description

7-0

EVTENA (Event Enable). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. Each bit enables system

notiﬁcation by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in GPEVST

0: Event pending by corresponding GPIO pin masked

1: Event pending by corresponding GPIO pin enabled

Bit

76543210

Name

EVTSTAT

Reset

00000000

Bit

Description

−0 EVTSTAT (Event Status). Bits 7−0 correspond to pins 7−0 of the speciﬁc Port. The setting of each bit is

independent of the Event Enable bit in GPEVEN register. An active event sets the Status bit, which may be

cleared only by software writing 1 to the bit.

0: No active edge or level detected since last cleared

1: Active edge or level detected

Bit

76543210

Name

DATAINOUT

Reset Write

11111111

Reset Read

XXXXXXXX

Bit

Description

7-0

DATAINOUT (Data In/Out). Bits 7-0 correspond to pins 7-0 of the speciﬁc Port. The value of each bit

determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit

latches the written data unless the bit is locked by the GPCFG register Lock bit. Reading each bit returns the

value of the corresponding GPIO pin. Pin conﬁguration and the data-out value may inﬂuence the pin value.

0: Corresponding pin driven to low; pin level read low.

1: Corresponding pin driven or released (according to buffer type selection) to high; pin level read high (default).

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