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WM8912 датащи(PDF) 112 Page - Cirrus Logic |
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WM8912 датащи(HTML) 112 Page - Cirrus Logic |
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112 / 129 page ![]() WM8912 Production Data w PD, Rev 4.1, February 2013 112 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R90 (5Ah) Analogue HP 0 7 HPL_RMV_SH ORT 0 Removes HPOUTL short 0 = HPOUTL short enabled 1 = HPOUTL short removed For normal operation, this bit should be set as the final step of the HPL Enable sequence. 6 HPL_ENA_OU TP 0 Enables HPOUTL output stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled. 5 HPL_ENA_DLY 0 Enables HPOUTL intermediate stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPL_ENA. 4 HPL_ENA 0 Enables HPOUTL input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the first step of the HPL Enable sequence. 3 HPR_RMV_SH ORT 0 Removes HPOUTR short 0 = HPOUTR short enabled 1 = HPOUTR short removed For normal operation, this bit should be set as the final step of the HPR Enable sequence. 2 HPR_ENA_OU TP 0 Enables HPOUTR output stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the DC offset cancellation has been scheduled. 1 HPR_ENA_DL Y 0 Enables HPOUTR intermediate stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set to 1 after the output signal path has been configured, and before DC offset cancellation is scheduled. This bit should be set with at least 20us delay after HPR_ENA. 0 HPR_ENA 0 Enables HPOUTR input stage 0 = Disabled 1 = Enabled For normal operation, this bit should be set as the first step of the HPR Enable sequence. Register 5Ah Analogue HP 0 |
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