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WM8912 датащи(PDF) 14 Page - Cirrus Logic |
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WM8912 датащи(HTML) 14 Page - Cirrus Logic |
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14 / 129 page ![]() WM8912 Production Data w PD, Rev 4.1, February 2013 14 SIGNAL TIMING REQUIREMENTS COMMON TEST CONDITIONS Unless otherwise stated, the following test conditions apply throughout the following sections: Ambient temperature = +25°C DCVDD = 1.0V DBVDD = AVDD = CPVDD = 1.8V DGND = AGND = CPGND = 0V Additional, specific test conditions are given within the relevant sections below. MASTER CLOCK Figure 1 Master Clock Timing Master Clock Timing PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT MCLK cycle time TMCLKY MCLK_DIV=1 40 ns MCLK_DIV=0 80 ns MCLK duty cycle TMCLKDS 60:40 40:60 |
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