WM8912 datasheet(66/129 Pages) CIRRUS

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WM8912

Production Data

PD, Rev 4.1, February 2013

The SYSCLK control register fields are defined in Table 39.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R22 (16h)

Clock Rates

MCLK_INV

MCLK Invert

0 = MCLK not inverted

1 = MCLK inverted

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK

1 = FLL output

CLK_SYS_ENA

System Clock enable

0 = Disabled

1 = Enabled

R20 (14h)

Clock Rates

MCLK_DIV

Enables divide by 2 on MCLK

0 = SYSCLK = MCLK

1 = SYSCLK = MCLK / 2

Table 39 MCLK and SYSCLK Control

CONTROL INTERFACE CLOCKING

has been set to 1, then a Master Clock must be present for control register Read/Write operations. If

CLK_SYS_ENA = 1 and MCLK is not present, then register access will be unsuccessful. (Note that

read/write access to register R22, containing CLK_SYS_ENA, is always possible.)

If it cannot be assured that MCLK is present when accessing the register map, then it is required to

set CLK_SYS_ENA = 0 to ensure correct operation.

Note that MCLK is always required when using HPOUTL, HPOUTR, LINEOUTL or LINEOUTR.

CLOCKING CONFIGURATION

The WM8912 supports a wide range of standard audio sample rates from 8kHz to 96kHz. The

Automatic Clocking Configuration simplifies the configuration of the clock dividers in the WM8912 by

deriving most of the required parameters from a minimum number of user registers.

The SAMPLE_RATE field selects the sample rate, fs, of the DAC.

The CLK_SYS_RATE fields must be set according to the ratio of SYSCLK to fs. When these fields

are set correctly, the Sample Rate Decoder circuit automatically determines the clocking configuration

for all other circuits within the WM8912.

A high performance mode of DAC operation can be selected by setting the DAC_OSR128 bit; in

48kHz sample mode, the DAC_OSR128 feature results in 128x oversampling. Audio performance is

improved, but power consumption is also increased.

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