WM8912 datasheet(55/129 Pages) CIRRUS

55 / 129 page

Production Data

WM8912

PD, Rev 4.1, February 2013

Note: The WM8912 is a 24-bit device. If the user operates the WM8912 in 32-bit mode then the 8

LSBs will be ignored on the DAC input. It is recommended to add a pull-down resistor to the DACDAT

line in TDM mode in this case.

BCLK FREQUENCY

The BCLK frequency is controlled relative to SYSCLK by the BCLK_DIV divider. Internal clock divide

and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a predictable

and repeatable position relative to each other and relative to the data for a given combination of DAC

sample rate and BCLK_DIV settings.

BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also “Clocking and Sample

Rates” section for more information.

AUDIO DATA FORMATS (NORMAL MODE)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 30 Right Justified Audio Interface (assuming n-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 31 Left Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.

The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and

the MSB of the next.

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