WM8912 datasheet(67/129 Pages) CIRRUS

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Production Data

WM8912

PD, Rev 4.1, February 2013

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R33 (21h)

DAC Digital

DAC_OSR128

DAC Oversample Rate Select

0 = Low power (normal OSR)

1 = High performance (double OSR)

R21 (15h)

Clock Rates

13:10

CLK_SYS_RAT

E [3:0]

0011

Selects the SYSCLK / fs ratio

0000 = 64

0001 = 128

0010 = 192

0011 = 256

0100 = 384

0101 = 512

0110 = 768

0111 = 1024

1000 = 1408

1001 = 1536

2:0

SAMPLE_RATE

[2:0]

101

Selects the Sample Rate (fs)

000 = 8kHz

001 = 11.025kHz, 12kHz

010 = 16kHz

011 = 22.05kHz, 24kHz

100 = 32kHz

101 = 44.1kHz, 48kHz

110 to 111 = Reserved

Table 40 Automatic Clocking Configuration Control

DAC CLOCK CONTROL

The clocking of the DAC circuits is derived from CLK_DSP, which is enabled by CLK_DSP_ENA.

CLK_DSP is generated from SYSCLK which is separately enabled, using the register bit

CLK_SYS_ENA.

Note that higher performance DAC operation can be achieved by increasing the DAC oversample

rate - see Table 40.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R22 (16h)

Clock Rates 2

CLK_DSP_ENA

DSP Clock enable

0 = Disabled

1 = Enabled

Table 41 ADC / DAC Clock Control

OPCLK CONTROL

A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled

by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV.

This output of this clock is also dependent upon the GPIO register settings described under “General

Purpose Input/Output (GPIO)”.

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