PC97338VLJ datasheet(167/221 Pages) NSC

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FIGURE 88. DMA Control Signals Routing

5.16.3 LCR/BSR – Link Control/Bank

Select Registers

These registers are the same as in bank 0.

5.16.4 EXCR2 – Extended Control

This register is used to configure the transmitter and

receiver FIFOs, and the baud generator prescaler.

Upon reset all bits are set to 0.

FIGURE 88. Extended Control Register 2

B1–0 TF_SIZ [1–0] – TX_FIFO Levels Select.

These bits select the number of levels for the

TX_FIFO.

They are effective only when the FIFOs are en-

abled.

Bits 1–0

TXFIFO Levels

Reserved

TX -

Routing

RX_DMA

Logic

Channel

DMA

Logic

RX -

Channel

DMA

Logic

TX_DMA

DMA

Hand-

shake

Signals

DMASWP

DMA Swap

Logic

Configuration

Module

321

Reset

Required

RF_SIZ0

PRESL0

PRESL1

Reserved

LOCK

TF_SIZ0

TF_SIZ1

RF_SIZ1

B3–2 RF_SIZ [1–0] – RX_FIFO Levels Select.

These bits select the number of levels for the

RX_FIFO.

They are effective only when the FIFOs are en-

abled.

Bits 3–2

RX_FIFO Levels

Reserved

B5–4 PRESL [1–0] – Prescaler Select.

The prescaler divides the 24 MHz input clock

frequency to provide the clock for the baud

generator.

Bits 5–4

Prescaler Value

13.0

1.625

Reserved

1.0

Reserved.

Read/write 0.

LOCK – Lock Bit.

When set to 1, accesses to the baud generator

divisor register through LBGD(L) and LBGD(H)

as well as fallback are disabled from non-ex-

tended mode.

In this case two scratchpad registers overlayed

with LBGD(L) and LBGD(H) are enabled, and

any attempted CPU access of the baud gener-

ator divisor register through LBGD(L) and LB-

GD(H) will access the scratchpad registers

instead. This bit must be set to 0 when extend-

ed mode is selected.

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