PC97338VLJ datasheet(171/221 Pages) NSC

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When a pipeline operation takes place, the following

occurs:

1. If the target mode is MIR or FIR, the transmitter is

halted for 250 s.

2. If the target mode is SIR, the transmitter is halted

for 250

µs or a character time (at the newly select-

ed baud rate), whichever is greater.

3. Bits 7, 6, 5 and 2 will be loaded into the corre-

sponding bit positions in the MCR register in bank

0, bit 3 will be loaded into bit position 3 of EXCR1.

Upon reset, all bits are set to 0.

FIGURE 88. Pipelined Mode Register

5.19.3 LCR/BSR – Link Control/Bank

Select Registers

These registers are the same as in bank 0.

5.19.4 IRCR2 – Infrared Control

Upon reset, the content of this register is 02h.

FIGURE 88. IInfrared Control Register 2

MD_PEN – Mode Bits Pipelining Enable.

When this bit is set to 1 and the transmitter be-

comes empty, a pipeline load operation takes

place.

This bit is automatically cleared after the load

has occurred.

BR_PEN – Baud Rate Pipelining Enable.

This bit is effective only when the MDPEN bit is

set to 1.

When it is set to 1 and a pipeline load operation

takes place, the PBGD register will be loaded

into the baud generator divisor register.

P_DMA_EN – Pipelined DMA Enable Bit

P_DMASWP – Pipelined DMA Swap Bit

Reserved.

Write 0.

B7–5 P_MDSL [2–0] – Pipelined Mode Select Bits

654

321

Reset

Required

P_DMA_EN

Reserved

P_MDSL0

P_MDSL1

P_MDSL2

MD_PEN

P_DMASWP

BR_PEN

B0 IR_FDPLX – Infrared Full Duplex Mode.

When set to 1, the infrared receiver is not masked

during transmission.

B1 IRMSSL – MSR Register Function Select in In-

frared Mode.

This bit selects the behavior of the modem status

lected. When UART mode is selected, the mo-

dem

status

and

interrupt

function

normally, and this bit is ignored.

→ MSR register and modem status interrupt

work as in UART mode.

→ MSR register returns 30h and the modem

status interrupt is disabled.

B2 MDRS – MIR Data Rate Select.

This bit determines the data rate in MIR mode.

→ 1.152 Mbps

→ 0.576 Mbps

B3 TX_MS – Transmitter Mode Select.

This bit is used in MIR and FIR modes only. When

it is set to 1, transmitter frame-end stop mode is

selected. In this case the transmitter stops after

transmission of a frame is complete, if the end-of-

frame condition was generated by the TFRCC

counter reaching 0. The transmitter can be re-

started by clearing the TXHFE bit in the ASCR

B4 AUX_IRRX – Auxiliary Infrared Input Select.

When set to 1, the infrared signal is received from

the auxiliary input. See Table 97.

B5 FEND_MD – Frame End Control.

This bit selects whether a terminal-count condi-

tion from the

TFRCC register will generate an EOF in PIO

mode or DMA mode.

→ TFRCC terminal count effective in PIO

mode.

321

Reset

Required

MDRS

AUX_IRRX

FEND_MD

SFTSL

Reserved

IR_FDPLX

IRMSSL

TX_MS

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