ADE9078ACPZ datasheet(106/108 Pages) AD

106 / 108 page

Data Sheet

ADE9078

Rev. 0| Page 105 of 107

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

0x4B4 CRC_FORCE

[15:1]

RESERVED

Reserved.

0x0

FORCE_CRC_UPDATE

Write this bit to force the configuration register

CRC calculation to start. When the calculation is

complete, the CRC_DONE bit is set in the

STATUS1 register.

0x0

R/W

0x4B5 CRC_OPTEN

CRC_WFB_TRG_CFG_EN

Set this bit to include the WFB_TRG_CFG register

in the configuration register CRC calculation.

0x0

R/W

CRC_WFB_PG_IRQEN

Set this bit to include the WFB_PG_IRQEN register

in the configuration register CRC calculation.

0x0

R/W

CRC_WFB_CFG_EN

Set this bit to include the WFB_CFG register in the

configuration register CRC calculation.

0x0

R/W

CRC_SEQ_CYC_EN

Set this bit to include the SEQ_CYC register in the

configuration register CRC calculation.

0x0

R/W

CRC_ZXLPSEL_EN

Set this bit to include the ZX_LP_SEL register in

the configuration register CRC calculation.

0x0

R/W

CRC_ZXTOUT_EN

Set this bit to include the CRC_ZXTOUT_EN

calculation.

0x0

R/W

CRC_APP_NL_LVL_EN

Set this bit to include the APP_NL_LVL register in

the configuration register CRC calculation.

0x0

R/W

CRC_REACT_NL_LVL_EN

Set this bit to include the REACT_NL_LVL register

in the configuration register CRC calculation.

0x0

R/W

CRC_ACT_NL_LVL_EN

Set this bit to include the ACT_NL_LVL register in

the configuration register CRC calculation.

0x0

R/W

[6:3]

RESERVED

Reserved.

0x0

CRC_EVENT_MASK_EN

Set this bit to include the EVENT_MASK register in

the configuration register CRC calculation.

0x0

R/W

CRC_MASK1_EN

Set this bit to include the MASK1 register in the

configuration register CRC calculation.

0x0

R/W

CRC_MASK0_EN

Set this bit to include the MASK0 register in the

configuration register CRC calculation.

0x0

R/W

0x4B8 PSM2_CFG

[15:9]

RESERVED

Reserved.

0x0

[8:5]

PKDET_LVL

These bits configure the PSM2 low power

comparator peak current detection Level, listed as

the input signal level with respect to full scale. The

returns to its default value if PSM0 is entered.

0x0

R/W

0000 100:1.

0001 200:1.

0010 300:1.

0011 400:1.

0100 500:1.

0101 600:1.

0110 700:1.

0111 800:1.

1000 900:1.

1001 1000:1.

1010 1100:1.

1011 1200:1.

ADE9078ACPZ датащи(PDF) 106 Page - Analog Devices

ADE9078ACPZ датащи(HTML) 106 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL