ADE9078ACPZ datasheet(92/108 Pages) AD

92 / 108 page

Data Sheet

ADE9078

Rev. 0| Page 91 of 107

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

REVPSUM3

This bit is set to indicate if the CF3 polarity

changed sign. See REVPSUM4.

0x0

R/W1

REVPSUM2

This bit is set to indicate if the CF2 polarity

changed sign. See REVPSUM4.

0x0

R/W1

REVPSUM1

This bit is set to indicate if the CF1 polarity

changed sign. See REVPSUM4.

0x0

R/W1

REVRPC

This bit indicates if the Phase C total or

fundamental reactive power has changed sign.

The PWR_SIGN_SEL bit in the EP_CFG register

selects whether total or fundamental reactive

power is monitored. This bit is updated when the

power values in the xVAR_ACC and xFVAR_ACC

registers have been updated, after PWR_TIME

4 kSPS samples.

0x0

R/W1

REVRPB

This bit indicates if the Phase B total or

fundamental reactive power has changed sign.

See REVRPC.

0x0

R/W1

REVRPA

This bit indicates if the Phase A total or

fundamental reactive power has changed sign.

See REVRPC.

0x0

R/W1

REVAPC

This bit indicates if the Phase C total active power

has changed sign. This bit is updated when the

power values in the xWATT_ACC and xWATT_ACC

registers have been updated, after PWR_TIME

4 kSPS samples.

0x0

R/W1

REVAPB

This bit indicates if the Phase B total active power

has changed sign. See REVAPC.

0x0

R/W1

REVAPA

This bit indicates if the Phase A total active power

has changed sign. See REVAPC.

0x0

R/W1

EGYRDY

This bit is set when the power values in the

xWATTHR, xVAHR, xVARHR, xFVARHR registers

have been updated, after EGY_TIME 4 kSPS

samples or line cycles, depending on the

EGY_TMR_MODE bit in the EP_CFG register.

0x0

R/W1

0x403 STATUS1

ERROR3

This bit indicates an error and generates a non-

maskable interrupt. Issue a software or hardware

reset to clear this error.

0x0

R/W1

ERROR2

This bit indicates that an error was detected and

corrected. No action is required.

0x0

R/W1

ERROR1

This bit indicates an error and generates a non-

maskable interrupt. Issue a software or hardware

reset to clear this error.

0x0

ERROR0

This bit indicates an error and generates a non-

maskable interrupt. Issue a software or hardware

reset to clear this error.

0x0

CRC_DONE

This bit is set to indicate when the configuration

writing the FORCE_CRC_UPDATE bit in the

CRC_FORCE register.

0x0

R/W1

CRC_CHG

This bit is set if any of the registers monitored by

the configuration register CRC change value. The

CRC_RSLT register holds the new configuration

0x0

R/W1

[25:19] RESERVED

Reserved.

0x0

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