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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADE9078ACPZ датащи(PDF) 84 Page - Analog Devices |
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ADE9078ACPZ датащи(HTML) 84 Page - Analog Devices |
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84 / 108 page  Data Sheet ADE9078 Rev. 0| Page 83 of 107 Addr. Name Description Len (Bits) Reset Access 0x401 VPEAK Voltage peak register. 32 0x00000000 R 0x402 STATUS0 Status Register 0. 32 0x00000000 R/W 0x403 STATUS1 Status Register 1. 32 0x00000000 R/W 0x404 EVENT_STATUS Event Status Register. 32 0x00000000 R 0x405 MASK0 Interrupt Enable Register 0. 32 0x00000000 R/W 0x406 MASK1 Interrupt Enable Register 1. 32 0x00000000 R/W 0x407 EVENT_MASK Event enable register. 32 0x00000000 R/W 0x40E USER_PERIOD User configured line period value used for resampling when the UPERIOD_SEL bit in the CONFIG2 register is set. 32 0x00500000 R/W 0x40F VLEVEL Register used in the algorithm that computes the fundamental reactive power. 32 0x00045D45 R/W 0x418 APERIOD Line period on Phase A voltage. 32 0x00A00000 R 0x419 BPERIOD Line period on Phase B voltage. 32 0x00A00000 R 0x41A CPERIOD Line period on Phase C voltage. 32 0x00A00000 R 0x41B COM_PERIOD Line period measurement on combined signal from Phase A, Phase B, and Phase C voltages. 32 0x00A00000 R 0x41C ACT_NL_LVL No load threshold in the total active power datapath. 32 0x0000FFFF R/W 0x41D REACT_NL_LVL No load threshold in the total and fundamental reactive power datapath. 32 0x0000FFFF R/W 0x41E APP_NL_LVL No load threshold in the total apparent power datapath. 32 0x0000FFFF R/W 0x41F PHNOLOAD Phase no load register. 32 0x00000000 R 0x420 WTHR Sets the maximum output rate from the digital to frequency converter for the total active power for the CF calibration pulse output. It is recommended to write WTHR = 0x0010 0000. 32 0x0000FFFF R/W 0x421 VARTHR Sets the maximum output rate from the digital to frequency converter for the total and fundamental reactive power for the CF calibration pulse output. It is recommended to write VARTHR = 0x0010 0000. 32 0x0000FFFF R/W 0x422 VATHR Sets the maximum output rate from the digital to frequency converter for the total apparent power for the CF calibration pulse output. It is recommended to write VATHR = 0x0010 0000. 32 0x0000FFFF R/W 0x423 LAST_DATA_32 This register holds the data read or written during the last 32-bit transaction on the SPI port. 32 0x00000000 R 0x424 ADC_REDIRECT This register allows any ADC output to be redirected to any digital datapath. 32 0x001FFFFF R/W 0x425 CF_LCFG CF calibration pulse width configuration register. 32 0x00000000 R/W 0x472 PART_ID This register identifies the IC. If the ADE9000_ID bit is 0, the IC is an ADE9078. 32 0x00000000 R 0x480 RUN Write this register to 1 to start the measurements. 16 0x0000 R/W 0x481 CONFIG1 Configuration Register 1. 16 0x0000 R/W 0x482 ANGL_VA_VB Time between positive to negative zero crossings on Phase A and Phase B voltages. 16 0x0000 R 0x483 ANGL_VB_VC Time between positive to negative zero crossings on Phase B and Phase C voltages. 16 0x0000 R 0x484 ANGL_VA_VC Time between positive to negative zero crossings on Phase A and Phase C voltages. 16 0x0000 R 0x485 ANGL_VA_IA Time between positive to negative zero crossings on Phase A voltage and current. 16 0x0000 R 0x486 ANGL_VB_IB Time between positive to negative zero crossings on Phase B voltage and current. 16 0x0000 R |
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