ADE9078ACPZ datasheet(75/108 Pages) AD

75 / 108 page

ADE9078

Data Sheet

Rev. 0 | Page 74 of 107

INTERRUPTS/EVENTS

The ADE9078 has three pins (IRQ0, IRQ1, and CF4/EVENT/

DREADY) that can be used as interrupts to the host processor.

The IRQ0 and IRQ1 pins go low when an enabled interrupt

occurs and stay low until the event is acknowledged by setting

the corresponding status bit in the STATUS0 and STATUS1

registers, respectively. The EVENT function, which is multiplexed

with the CF4 and DREADY options on the CF4/EVENT/

DREADY pin, tracks the state of the enabled signals and goes

low and high with these internal signals. The EVENT function is

especially useful for measuring the duration of events, such as

no load, externally.

INTERRUPTS (IRQ0 AND IRQ1)

The IRQ0 and IRQ1 pins are managed by 32-bit interrupt mask

registers, MASK0 and MASK1, respectively. Every event that

can generate an interrupt has a corresponding bit in the MASK0

or MASK1 register and STATUS0 or STATUS1 register.

To enable an interrupt, set the corresponding bit in the MASK0

or MASK1 register. To disable an interrupt, the corresponding

bit in MASK0 or MASK1 must be cleared.

The STATUS0 and STATUS1 registers indicate if an event that

can generate an interrupt has occurred. If the corresponding bit

in the MASK0 or MASK1 register is set, an interrupt is generated

on the corresponding IRQ0 or IRQ1 pin, and the pin goes low.

To determine the source of the interrupt, read the corresponding

STATUS0 or STATUS1 register and identify which enabled bits

are set to 1. To acknowledge the event and clear bits in the

STATUSx register, write to the STATUSx register with the

desired bit positions set to 1. Then, the corresponding IRQ0 or

IRQ1 pin goes high.

For example, if a zero crossing occurs on the Phase A voltage input

and the ZXVA bit is set in the MASK1 register, the IRQ1 pin goes

low, indicating that an enabled event has occurred. To acknowledge

the event, write a 1 to the ZXVA bit in the STATUS1 register and

then the IRQ1 goes high. The ZXVA bit in the STATUS1 register is

set regardless of whether the ZXVA bit is enabled in the MASK1

There are a few interrupts that are nonmaskable, meaning that

they are generated even if the corresponding bit in the MASKx

and ERROR0.

There is an option to combine all the interrupts onto a single

interrupt pin, IRQ1, instead of using two pins, IRQ0 and IRQ1.

To activate this option, set the IRQ0_ON_IRQ1 bit in the

CONFIG1 register. When IRQ0_ON_IRQ1 = 1, IRQ1 indicates

both IRQ0 and IRQ1 events, and IRQ0 indicates IRQ0 events.

EVENT

The EVENT function is multiplexed with CF4 and DREADY on

the CF4/EVENT/DREADY pin. To enable the EVENT function

to be output on this pin, write CF4_CFG = 10 in the CONFIG1

The EVENT_MASK register manages which signals are

incorporated into the EVENT pin. All of these events sources

are maskable and disabled by default.

Events are enabled by setting the corresponding mask bit to 1 in

the EVENT_MASK register. The EVENT pin goes low whenever

one of the enabled events occurs and stay lows until all the enabled

signals go high. Then, the EVENT pin goes high. The logic level

of the EVENT output is solely dependent on the enabled events;

it cannot be changed by the user. Note that the status sources that

generate the EVENT signal are not latched—if one event source is

selected, the EVENT pin tracks the status of that source.

STATUS BITS IN ADDITIONAL REGISTERS

Several interrupts are used in conjunction with other status

registers.

No Load

The RFNOLOAD, VANLOAD, and ANLOAD bits in the

MASK1 register function in conjunction with additional status

bits in the PHNOLOAD register.

The following bits in the MASK0 register work with the status

bits in the PHSIGN register: REVAPx, REVRPx, and REVPSUMx

See Table 32 for more information when the corresponding bits

are set in the STATUSx register.

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