ADE9078ACPZ datasheet(94/108 Pages) AD

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Data Sheet

ADE9078

Rev. 0| Page 93 of 107

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

0x404 EVENT_STATUS [31:17] RESERVED

Reserved.

0x0

DREADY

This bit changes from a one to a zero when new

waveform samples are ready. The update rate

depends on the data selected in the WF_SRC bits

in the WFB_CFG register.

0x0

RESERVED

Reserved.

0x0

RFNOLOAD

This bit is set when the fundamental reactive

energy accumulations in all phases are out of no

load. This bit goes to zero when one or more

phases of fundamental reactive energy

accumulation goes into no load.

0x0

RESERVED

Reserved.

0x0

VANLOAD

This bit is set when the total apparent energy

accumulations in all phases are out of no load. This

bit goes to zero when one or more phases of total

apparent energy accumulation goes into no load.

0x0

RNLOAD

This bit is set when the total reactive energy

accumulations in all phases are out of no load. This

bit goes to zero when one or more phases of total

reactive energy accumulation goes into no load.

0x0

ANLOAD

This bit is set when the total active energy

accumulations in all phases are out of no load. This

bit goes to zero when one or more phases of total

active energy accumulation goes into no load.

0x0

REVPSUM4

This bit indicates the sign of the last CF4 pulse. A

zero indicates that the pulse was from negative

energy and a one indicates that the energy was

positive. This bit is updated when a CF4 pulse is

output, when the CF4 pin goes from high to low.

0x0

REVPSUM3

This bit indicates the sign of the last CF3 pulse. A

zero indicates that the pulse was from negative

energy and a one indicates that the energy was

positive. This bit is updated when a CF3 pulse is

output, when the CF3 pin goes from high to low.

0x0

REVPSUM2

This bit indicates the sign of the last CF2 pulse. A

zero indicates that the pulse was from negative

energy and a one indicates that the energy was

positive. This bit is updated when a CF2 pulse is

output, when the CF2 pin goes from high to low.

0x0

REVPSUM1

This bit indicates the sign of the last CF1 pulse. A

zero indicates that the pulse was from negative

energy and a one indicates that the energy was

positive. This bit is updated when a CF1 pulse is

output, when the CF1 pin goes from high to low.

0x0

[5:0]

RESERVED

Reserved.

0x0

0x405 MASK0

[31:25] RESERVED

Reserved.

0x0

MISMTCH

Set this bit to enable an interrupt when there is a

change in the relationship between ISUMRMS and

ISUMLVL.

0x0

R/W

COH_WFB_FULL

Set this bit to enable an interrupt when the

waveform buffer is full with resampled data, which

is selected when WF_CAP_SEL = 0 in the WFB_CFG

0x0

R/W

WFB_TRIG

Set this bit to enable an interrupt when one of the

events configured in WFB_TRIG_CFG occurs.

0x0

R/W

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