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ADE9078ACPZ датащи(PDF) 104 Page - Analog Devices

номер детали ADE9078ACPZ
подробное описание детали  High Performance
PDF  108 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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ADE9078ACPZ датащи(HTML) 104 Page - Analog Devices

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Data Sheet
ADE9078
Rev. 0| Page 103 of 107
Addr. Name
Bits
Bit Name
Settings Description
Reset
Access
4
WF_CAP_EN
When this bit is set, a waveform capture is started. 0x0
R/W
0 The waveform capture is disabled. The waveform
buffer contents are maintained.
1 The waveform capture is started, according to the
type of capture in WF_CAP_SEL and the WF_SRC
bits when this bit goes from a 0 to a 1.
[3:0]
BURST_CHAN
Selects which data to read out of the waveform
buffer through SPI.
0x0
R/W
0000 All channels.
0001 IA and VA.
0010 IB and VB.
0011 IC and VC.
1000 IA.
1001 VA.
1010 IB.
1011 VB.
1100 IC.
1101 VC.
1110 IN if WF_IN_EN = 1 in the WFB_CFG register.
1111 Single address read (SPI burst read mode is
disabled).
0x4A2 WFB_TRG_CFG [15:11] RESERVED
Reserved.
0x0
R
10
TRIG_FORCE
Set this bit to trigger an event to stop the
waveform buffer filling.
0x0
R/W
9
ZXCOMB
Zero crossing on combined signal from VA, VB, and
VC.
0x0
R/W
ZXVC
Phase C voltage zero crossing.
0x0
R/W
7
ZXVB
Phase B voltage zero crossing.
0x0
R/W
6
ZXVA
Phase A voltage zero crossing.
0x0
R/W
5
ZXIC
Phase C current zero crossing.
0x0
R/W
4
ZXIB
Phase B current zero crossing.
0x0
R/W
3
ZXIA
Phase A current zero crossing.
0x0
R/W
[2:0]
RESERVED
Reserved.
0x0
R
0x4A3 WFB_TRG_STAT [15:12] WFB_LAST_PAGE
These bits indicate which page of the Waveform
Buffer was filled last, when filling with Fixed Rate
Data samples.
0x0
R/W
11
RESERVED
Reserved.
0x0
R
[10:0]
WFB_TRIG_ADDR
This holds the address of the last sample put into
the waveform buffer after a trigger event occurred,
which is within a sample or two of when the actual
trigger event occurred.
0x0
R
0x4AF CONFIG2
[15:13] RESERVED
Reserved.
0x0
R
12
UPERIOD_SEL
Set this bit to use a user configured line period, in
USER_PERIOD, for the resampling calculation. If
this bit is clear, the phase voltage line period
selected by the LP_SEL[1:0] bits in the ZX_LP_SEL
register is used.
0x0
R/W



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