ADE9078ACPZ datasheet(66/108 Pages) AD

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Data Sheet

ADE9078

Rev. 0 | Page 65 of 107

Note that the LAST_DATA_16 and LAST_DATA_32 registers

are not updated after a SPI burst read operation—these registers

are the cases in Table 25 where the next address is written.

On a write operation, LAST_DATA_16 and LAST_DATA_32

are not updated until all 16 or 32 bits of the write data are received.

Note that, on a write register operation, the addressed register is

not written until all 16 or 32 bits are received, depending on the

length of the register.

Note that when the LAST_CMD, LAST_DATA_16, and

LAST_DATA_32 registers are read, their values remain

unchanged.

CRC OF CONFIGURATION REGISTERS

The configuration register CRC feature in the ADE9078 monitors

certain external and internal register values. It also optionally

includes 12 registers that are individually selectable in the

CRC_OPTEN register. See the CRC_OPTEN register in Table 32

for more details.

This feature runs as a background task—it takes 10.8 ms to

calculate the configuration register CRC. The result is stored in

the CRC_RSLT register. If any of the monitored registers change

value, the CRC_RSLT register changes as well, and the

CRC_CHG bit in the STATUS 1 register is set, which can also

be configured to generate an interrupt on IRQ1.

After configuring the ADE9078 and writing the required

registers to calibrate the measurements, such as xIGAIN or

xVGAIN, the configuration register CRC calculation can be

started by writing the FORCE_CRC_UPDATE bit in the

CRC_FORCE register. When the calculation is complete, the

CRC_DONE bit is set in the STATUS1 register.

The method used for calculating the configuration register CRC is

also based on the CRC-16 CCITT algorithm. The most significant

byte of each register is introduced into the LFSR first, without

bit reversal (see the CRC Algorithm section for more

information).

The order in which the registers are calculated is given in Table 26,

with the lowest register introduced first. Note that 32-bit registers

have four bytes introduced into the LFSR, whereas 16-bit

registers have two bytes introduced into the LFSR.

Note that the default value of certain internal registers can vary

for each device and, thus, the default CRC of configuration

registers can vary for each device.

Table 26. Order of Registers Included in the Configuration

0x01 to 0x18

0x21 to 0x38

0x41 to 0x58

0x60 to 0x73

0x409

0x40F

0x420 to 0x422

0x424

0x470 to 0x475

0x480 to 0x481

0x490 to 0x497

0x499

0x4AF to 0x4B2

0x425

0x4B8 to 0x4B9

0x47D

0x478 to 0x479

0x4EF

0x4BA

0x47E

0x00

0x20

0x40

0x4B6

0x4BF

0x4B5

CONFIGURATION LOCK

The configuration lock feature prevents changes to the ADE9078

configuration. To enable this feature, write 0x3C64 to the

WR_LOCK register. To disable the feature, write 0x4AD1.

To determine whether this feature is active, read the

WR_LOCK register, which reads as 1 if the protection is

enabled and 0 if it is disabled.

When this feature is enabled, it prevents writing to Address 0x000

to Address 0x0FF and Address 0x400 to Address 0x4FF.

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