ADE9078ACPZ datasheet(68/108 Pages) AD

68 / 108 page

Data Sheet

ADE9078

Rev. 0 | Page 67 of 107

xVGAIN

HPF

VOLTAGE PEAK

DETECTION

REFERENCE

VIN

+1V

ANALOG INPUT RANGE

–1V

ADE9078 VOLTAGE CHANNEL

SINC4

LPF

4:1

WF_SRC

WF_CAP_SEL

HPFDIS

TOTAL ACTIVE AND

REACTIVE POWER

CALCULATION

ZX_SRC_SEL

TOTAL VOLTAGE RMS

VA POWER

CALCULATIONS

FUNDAMENTAL

REACTIVE POWER

CALCULATIONS

NOTE: VCONSEL SUPPORTS SEVERAL 3-WIRE AND 4-WIRE HARDWARE CONFIGURATIONS

100

VA = VA – VB;

VB = VA – VC;

VC = VC – VB;

VB = –VA

VB = –VA – VC

VB = VA – VC

011

010

001

000

RESAMPLED WAVEFORM

RANGE

0xFBFF_FB90 =

–67,110,000

0x0471_15C0 =

+74,520,000

0x0474_E650 =

+74,770,000

VOLTAGE CHANNE L (xV_PCF)

DATA RANGE

SINC4 + IIR LPF (xV_LPF_DAT)

DATA RANGE

SINC4 OUTPUT (xV_SINC_DAT)

DATA RANGE

0x0400_0470 =

+67,110,000

0x46B4 =

+18,100

0xB94C =

–18,100

0xFB8B_19B0 =

–74,770,000

0xFB8E_EA40 =

–74,520,000

WAVEFORM

BUFFER

RESAMPLING

VCONSEL*

4 kSPS

NOT AVAILABLE IN ADE9078 PSM1

Figure 105. Voltage Channel Datapath

FIXED DATA RATE WAVEFORMS

Fixed data rate waveforms from the signal chain can be stored

into the waveform buffer from the sources shown in Table 27.

Table 27. Fixed Data Rate Waveform Sources

Source

WF_SRC

Data Rate

(kSPS)

32-Bit Data

Format

Sinc4 Outputs

According to

Figure 106

Sinc4 + IIR LPF

Output

According to

Figure 106

Waveforms

Processed by the

DSP (xI_PCF,

xV_PCF)

5.27 format

The 24-bit sinc4 and sinc4 + IIR LPF data is stored as 32 bits in

the waveform buffer by shifting left by 4 bits and sign extended.

ADC_DATA[23:0]

0000

Figure 106. Format for the ADC Data Stored in the Waveform Buffer,

x_SINC_DAT, and x_LPF_DAT Registers

Table 27 indicates the WF_SRC selection for each fixed data rate

waveform source. Each fixed data rate sample is 32-bit; however,

the data format varies between the three sources, as indicated in

Table 27. When the waveform buffer is enabled, the data from all

seven channels is stored into the buffer. One sample set consists of

one sample per channel, seven samples total, which are taken at

the same point in time.

Figure 107 shows how the fixed data rate samples are stored into

the buffer. Every sample set is separated in memory from the

adjacent one by the use of spare cells, which do not contain any

sample data, as shown in Figure 107. In this way, every eighth

32-bit memory location in the buffer is reserved as a spare cell.

If the seventh channel is disabled, with the WF_IN_EN bit in

the WFB_CFG register = 0, the IN sample locations are treated

as spare cells as well.

0 xFFF

IN, IF WFB_CFG.WF_IN_EN = 1

SPARE CELL, IF WFB_CFG.WF_IN_EN = 0

SPARE CELL

0x807

0x806

0x805

0x804

0x803

0x802

0x801

0x800

Figure 107. Fixed Data Rate Waveform Sample Storage

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