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PC87413 датащи(PDF) 254 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 254 Page - National Semiconductor (TI) |
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254 / 257 page ![]() 11.0 Device Characteristics (Continued) www.national.com 254 Revision1.2 Figure 68. Resume by SLPS3, SLPS5, After Power Fail (No VBAT) Wake-Up Inputs at VDD Power Switching Figure 69. Wake-Up Inputs at VDD Power Switching (VDDFELL Enabled) Symbol Figure Description Reference Conditions Min Max tEWIV 69 External Wake-up inputs valid1 1. Not tested. Guaranteed by design. After VDD power On 1 s 1.25 s tVDFH 69 VDDFELL high time1 After VDD power Off 1 s 1.25 s tKBMID 69 Keyboard and Mouse Wake- up inputs disable1 After VDD power Off, if VDDFELL is enabled 2 s 2.25 s VSB (Power) tEWIV VSBOFF VSBON (Internal) VSB Power-Up Reset 32 KHz Clock (internal) t32KW tIRST SLPS3, SLPS5 ONCTL TRI-STATE PWBTOUT TRI-STATE tPBOP VDD (Power) VDDFELL GPIOE10-17, tEWIV GPIOE40-47 KBCLK, MCLK VDDOFF VDDON tVDFH tKBMID KBDAT, MDAT (VDDLOAD = 1) |
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