COP888EB datasheet(18/75 Pages) NSC

18 / 75 page

Timers (Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

Mode

TxC3

TxC2

TxC1

Description

Interrupt A

Source

Interrupt B

Source

Timer

Counts On

PWM: TxA Toggle

Autoreload RA

Autoreload RB

PWM: No TxA

Toggle

Autoreload RA

Autoreload RB

External Event

Counter

Timer

Underflow

Pos. TxB Edge

Pos. TxA

Edge

External Event

Counter

Timer

Underflow

Pos. TxB Edge

Pos. TxA

Edge

Captures:

Pos. TxA Edge

Pos. TxB Edge

TxA Pos. Edge

or Timer

TxB Pos. Edge

Underflow

Captures:

Pos. TxA

Neg. TxB

TxA Pos. Edge

Edge or Timer

Edge

TxB Neg. Edge

Underflow

Captures:

Neg. TxA

Neg. TxB

TxA Neg. Edge

Edge or Timer

Edge

TxB Neg. Edge

Underflow

Captures:

Neg. TxA

Neg. TxB

TxA Neg. Edge

Edge or Timer

Edge

TxB Neg. Edge

Underflow

Power Save Modes

The device offer the user two power save modes of opera-

tion: HALT and IDLE. In the HALT mode, all microcontroller

activities are stopped. In the IDLE mode, the on-board oscil-

lator circuitry and timer T0 are active but all other microcon-

troller activities are stopped. In either mode, all on-board

RAM, registers, I/O states, and timers (with the exception of

T0) are unaltered.

HALT MODE

The device is placed in the HALT mode by writing a ’’1” to the

HALT flag (G7 data bit). All microcontroller activities, includ-

ing the clock, and timers, are stopped. In the HALT mode,

the power requirements of the device are minimal and the

applied voltage (V

CC) may be decreased to Vr (Vr = 2.0V)

without altering the state of the machine.

CAN HALT/IDLE mode:

In order to reduce the device overall current consumption in

HALT/IDLE mode a two step power save mechanism is

implemented on the device:

Step 1:

Disable main receive comparator. This is done by

resetting both the TxEN0 and TxEN1 bits in the

CBUS register. Note: These bits should always be

reset before entering HALT/IDLE mode to allow

proper resynchronization to the CAN bus after ex-

iting HALT/IDLE mode.

Step 2:

Disable the CAN wake-up comparators, this is

done by resetting bit 7 in the port-m wakeup en-

able register (MWKEN) a transition on the CAN

bus will then not wake the device up.

Note: If both the main receive comparator and the wake-up comparator are

disabled the on chip CAN voltage reference is also disabled. The CAN-

VREF output is then High-Z

The following table shows the two CAN power save modes and the active CAN transceiver blocks:

Step 1

Step 2

Main-Comp

Wake-Up-Comp

CAN-V

REF

REF Pin

CC/2

off

CC/2

off

CC/2

off

High-Z

The device supports two different ways of exiting the HALT

mode. The first method of exiting the HALT mode is with the

Multi-Input Wakeup feature on the L & M port. The second

method of exiting the HALT mode is by pulling the RESET

pin low.

Since a crystal or ceramic resonator may be selected as the

oscillator, the Wakeup signal is not allowed to start the chip

running immediately since crystal oscillators and ceramic

resonators have a delayed start up time to reach full ampli-

tude and frequency stability. The IDLE timer is used to gen-

erate a fixed delay to ensure that the oscillator has indeed

stabilized before allowing instruction execution. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry is enabled. The IDLE timer is loaded with a value of

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