COP888EB datasheet(24/75 Pages) NSC

24 / 75 page

Functional Block Description of the CAN Interface (Continued)

In the case of an interrupt driven CAN interface, the calcula-

tion of the actual t

LOAD time would be done as follows:

INT:

;Interrupt latency = 7tc=7µs

PUSH A

; 3tc=3µs

A,B;2tc=2µs

PUSH A

; 3tc=3µs

VIS

;5tc=5µs

CANTX:

;20tc = µs to this point

•

;additional time for instructions

;which check

•

;status prior to reloading the

;transmit data

•

;registers with subsequent data

;bytes.

TXD2,DATA

•

Interrupt driven programs use more time than programs

which poll the TBE flag, however programs which operate at

lower baud rates (which are more likely to be sensitive to this

issue) have more time for interrupt response.

Output Drivers/Input Comparators

The output drivers/input comparators are the physical inter-

face to the bus. Control bits are provided to TRI-STATE the

output drivers.

A dominant bit on the bus is represented as a “0” in the data

registers and a recessive bit on the bus is represented as a

“1” in the data registers.

TABLE 4. Bus Level Definition

Bus Level

Pin Tx0

Pin Tx1

Data

“dominant”

drive low

dirve high

(GND)

CC)

“recessive”

TRI-STATE

The register block consists of fifteen 8-bit registers which are

described in more detail in the following paragraphs.

Note: The contents of the receiver related registers RxD1, RxD2, RDLC,

RIDH and RTSTAT are only changed if a received frame passes the

acceptance filter or the Receive Identifier Acceptance Filter bit (RIAF)

is set to accept all received messages.

TRANSMIT DATA REGISTER 1 (TXD1)(Address X’00A0)

The Transmit Data Register 1 contains the first data byte to

be transmitted within a frame and then the successive odd

byte numbers (i.e., bytes number 1,3,..,7).

TRANSMIT DATA REGISTER 2 (TXD2)(Address X’00A1)

The Transit Data Register 2 contains the second data byte to

be transmitted within a frame and then the successive even

byte numbers (i.e., bytes number 2,4,..,8).

TRANSMIT DATA LENGTH CODE AND IDENTIFIER

LOW REGISTER (TDLC)(Address X’00A2)

TID3

TID2

TID1

TID0

TDLC3

TDLC2

TDLC1

TDLC0

Bit 7

Bit 0

This register is read/write.

TID3..TIDO

Transmit Identifier Bits 3..0 (lower 4 bits)

The transmit identifier is composed of eleven bits in total, bits

3 to 0 of the TID are stored in bits 7 to 4 of this register.

TDLC3..TDLC0 Transmit Data Length Code

These bits determine the number of data bytes to be trans-

mitted within a frame. The CAN specification allows a maxi-

mum of eight data bytes in any message.

TRANSMIT IDENTIFIER HIGH (TID)(Address X’00A3)

TRTR

TID10

TID9

TID8

TID7

TID6

TID5

TID4

Bit 7

Bit 0

This register is read/write.

TRTR

Transmit Remote Frame Request

This bit is set if the frame to be transmitted is a remote frame

request.

TID10..TID4

Transmit Identifier Bits 10 .. 4 (higher 7 bits)

Bits TID10..TID4 are the upper 7 bits of the 11 bit transmit

identifier.

RECEIVER DATA REGISTER 1 (RXD1)(Address X’00A4)

The Receive Data Register 1 (RXD1) contains the first data

byte received in a frame and then successive odd byte num-

bers (i.e., bytes 1, 3,..7). This register is read-only.

RECEIVE DATA REGISTER 2 (RXD2)(Address X’00A5)

The Receive Data Register 2 (RXD2) contains the second

data byte received in a frame and then successive even byte

numbers (i.e., bytes 2,4,..,8). This register is read-only.

DS012837-18

FIGURE 16. TBE Timing

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