COP888EB datasheet(15/75 Pages) NSC

15 / 75 page

Control Registers (Continued)

The ICNTRL register contains the following bits:

Reserved This bit is reserved and should be zero

LPEN

L Port/M Port Interrupt Enable (Multi-Input

Wakeup/Interrupt)

T0PND Timer T0 Interrupt pending

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

µWPND MICROWIRE/PLUS interrupt pending

µWEN

Enable MICROWIRE/PLUS interrupt

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture

edge

T1ENB Timer T1 Interrupt Enable for T1B Input capture

edge

T2CNTRL Register (Address X'00C6)

T2C3

T2C2

T2C1

T2C0

T2PNDA

T2ENA

T2PNDB

T2ENB

Bit 7

Bit 0

The T2CNTRL control register contains the following bits:

T2C3

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C1

Timer T2 mode control bit

T2C0

Timer

Start/Stop

control

timer

modes 1 and 2, T2 Underflow Interrupt Pend-

ing Flag in timer mode 3

T2PNDA

Timer T2 Interrupt Pending Flag (Autoreload

RA in mode 1, T2 Underflow in mode 2, T2A

capture edge in mode 3)

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

T2PNDB

Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

T2ENB

Timer T2 Interrupt Enable for Timer Underflow

or T2B Input capture edge

Timers

The device contains a very versatile set of timers (T0, T1 and

T2). All timers and associated autoreload/capture registers

power up containing random data.

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE timer T0, which is a

16-bit timer. The Timer T0 runs continuously at the fixed rate

of the instruction cycle clock, t

c. The user cannot read or

write to the IDLE Timer T0, which is a count down timer.

The Timer T0 supports the following functions:

•

Exit out of the Idle Mode (See Idle Mode description)

•

WATCHDOG logic (See WATCHDOG description)

•

Start up delay out of the HALT mode

Figure 8 is a functional block diagram showing the structure

of the IDLE Timer and its associated interrupt logic.

Bits 11 through 15 of the ITMR register can be selected for

triggering the IDLE Timer interrupt. Each time the selected

bit underflows (every 4k, 8k, 16k, 32k or 64k instruction

cycles), the IDLE Timer interrupt pending bit T0PND is set,

thus generating an interrupt (if enabled), and bit 6 of the Port

G data register is reset, thus causing an exit from the IDLE

mode if the device is in that mode.

In order for an interrupt to be generated, the IDLE Timer in-

terrupt enable bit T0EN must be set, and the GIE (Global In-

terrupt Enable) bit must also be set. The T0PND flag and

T0EN bit are bits 5 and 4 of the ICNTRL register, respec-

tively. The interrupt can be used for any purpose. Typically, it

is used to perform a task upon exit from the IDLE mode. For

more information on the IDLE mode, refer to the Power Save

Modes section.

The Idle Timer period is selected by bits 0–2 of the ITMR

should not be used as software flags.

ITMR Register (Address X’0xCF)

Reserved

ITSEL2

ITSEL1

ITSLE0

Bit 7

Bit 0

TABLE 2. Idle Timer Window Length

ITSEL2

ITSEL1

ITSEL0

Idle Timer Period

(Instruction Cycles)

4,096

8,192

16,384

32,768

65,536

The ITMR register is cleared on Reset and the Idle Timer pe-

riod is reset to 4,096 instruction cycles.

Any time the IDLE Timer period is changed there is the pos-

sibility of generating a spurious IDLE Timer interrupt by set-

ting the T0PND bit. The user is advised to disable IDLE

Timer interrupts prior to changing the value of the ITSEL bits

of the ITMR Register and then clear the T0PND bit before at-

tempting to synchronize operation to the IDLE Timer.

TIMER T1 and TIMER T2

The device has a set of three powerful timer/counter blocks,

T1 and T2. The associated features and functioning of a

timer block are described by referring to the timer block Tx.

Since the three timer blocks, T1 and T2 are identical, all

comments are equally applicable to either of the three timer

blocks.

Each timer block consists of a 16-bit timer, Tx, and two sup-

porting 16-bit autoreload/capture registers, RxA and RxB.

Each timer block has two pins associated with it, TxA and

DS012837-9

FIGURE 8. Functional Block Diagram for Idle Timer T0

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