COP888EB datasheet(27/75 Pages) NSC

27 / 75 page

Functional Block Description of

the CAN Interface (Continued)

an interrupt by setting the Transmit Interrupt Enable bit (TIE).

When servicing the interrupt the user has to make sure that

TBE gets cleared by executing a WRITE instruction on the

TxD2 register, otherwise a new interrupt will be generated

immediately after return from the interrupt service routine.

The TBE bit is read only. It is set to 1 upon reset. TBE is also

set upon completion of transmission of a valid message.

TXPND

Transmission Pending

This bit is set as soon as the Transmit Start/Stop (TXSS) bit

is set by the user. It will stay set until the frame was success-

fully transmitted, until the transmission was successfully can-

celed by writing zero to the Transmission Start/Stop bit

(TXSS), or the device enters the bus-off state. Resetting the

TXSS bit will only cancel a transmission if the transmission

of a frame hasn’t been started yet (bus idle) or if arbitration

has been lost (receiving). If the device has already started

transmission (won arbitration) the TXPND flag will stay set

until the transmission is completed, even if the user’s soft-

ware has requested cancellation of the message. If an error

occurs during transmission, a requested cancellation may

occur prior to the begining of retransmission.

RRTR

Received Remote Transmission Request

This bit is set when the remote transmission request (RTR)

bit in a received frame was set. It is automatically reset

through a read of the RXD1 register.

To detect RRTR the user can either poll this flag or enable

the receive interrupt (the reception of a remote transmission

request will also cause an interrupt if the receive interrupt is

enabled). If the receive interrupt is enabled, the user should

check the RRTR flag in the service routine in order to distin-

guish between a RRTR interrupt and a RBF interrupt. It is the

responsibility of the user to clear this bit by reading the RXD1

ROLD

Received Overload Frame

This bit is automatically set when an Overload Frame was

received on the bus. It is automatically reset through a read

of the Receive/Transmit Status register. It is the responsibil-

ity of the user to clear this bit by reading the Receive/

Transmit Status register, before the next frame is received.

RORN

Receiver Overrun

This bit is automatically set on an overrun of the receive data

RxDn registers when receiving a frame. It it automatically re-

set through a read of the Receive/Transmit Status register. It

is the responsibility of the user to clear this bit by reading the

Receive/Transmit Status register before the next frame is re-

ceived.

RFV

Received Frame Valid

This bit is set if the received frame is valid, i.e., after the pen-

ultimate bit of the End of Frame is received. It is automati-

cally reset through a read of the Receive/Transmit Status

reading the receive/transmit status register (RTSTAT), be-

fore the next frame is received. RFV will cause a Receive In-

terrupt if enabled by RIE. The user should be careful to read

the last data byte (RxD1) of odd length messages (1, 3, 5 or

7 data bytes) on receipt of RFV. RFV is the only indication

that the last byte of the message has been received.

RCV

Receive Mode

This bit is set after the data length code of a message that

passes the device’s acceptance filter has been received. It is

automatically reset after the CRC-delimiter of the same

frame has been received. It indicates to the user’s software

that arbitration is lost and that data is coming in for that node.

RBF

Receive Buffer Full

This bit is set if the second Rx data byte was received. It is

reset automatically, after the RxD1-Register has been read

by the software. RBF can be programmed to generate an in-

terrupt by setting the Receive Interrupt Enable bit (RIE).

When servicing the interrupt, the user has to make sure that

RBF gets cleared by executing a LD instruction from the

RxD1 register, otherwise a new interrupt will be generated

immediately after return from the interrupt service routine.

The RBF bit is read only.

TRANSMIT ERROR COUNTER (TEC) (Address X’00AD)

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

Bit 7

Bit 0

This register is read/write.

For test purposes and to identify the node status, the trans-

mit error counter, an 8-bit error counter, is mapped into the

data memory. If the lower seven bits of the counter overflow,

i.e., TEC7 is set, the device is error passive.

CAUTION

To prevent interference with the CAN fault confinement, the

user must not write to the REC/TEC registers. Both counters

are automatically updated following the CAN specification.

RECEIVE ERROR COUNTER (REC) (00AE)

ROVL

REC6

REC5

REC4

REC3

REC2

REC1

REC0

Bit 7

Bit 0

This register is read/write.

ROVL

receive error counter overflow

For test purposes and to identify the node status the receive

error counter, a 7-bit error counter, is mapped into the data

memory. If the counter overflows the ROVL bit is set to indi-

cate that the device is error passive and won’t transmit any

active error frames. If ROVL is set then the counter is frozen.

MESSAGE IDENTIFICATION

a. Transmitted Message

The user can select all 11 Transmit Identifier Bits to transmit

any message whigh fulfills the CAN2.0, part B spec without

an extended identifier (see note below). Fully automatic re-

transmission is supported for messages no longer than 2

bytes.

b. Received Messages

The lower four bits of the Receive Identifier are don’t care,

i.e., the controller will receive all messages that fit in that win-

dow (16 messages). The upper 7 bits can be defined by the

user in the Receive Identifier High Register to mask out

groups of messages. If the RIAF bit is set, all messages will

be received.

Note: The CAN interface tolerates the extended CAN frame format of 29

identifier bits and gives an acknowledgment. If an error occurs the re-

ceive error counter will be increased, and decreased if the frame is

valid.

BUS SYNCHRONIZATION DURING OPERATION

Resetting the TxEN1 and TxEN0 bits in Bus Control Register

will disable the output drivers and do a resynchronization to

the bus. All other CAN related registers and flags will be un-

affected.

COP888EB датащи(PDF) 27 Page - National Semiconductor (TI)

COP888EB датащи(HTML) 27 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

датащи скачать

ссылки URL