COP888EB datasheet(59/75 Pages) NSC

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USART Operation (Continued)

Note that the XBIT9/PSEL0 bit located in the ENU register

serves two mutually exclusive functions. This bit programs

the ninth bit for transmission when the USART is operating

with nine data bits per frame. There is no parity selection in

this framing format. For other framing formats XBIT9 is not

needed and the bit is PSEL0 used in conjunction with PSEL1

to select parity.

The frame formats for the receiver differ form the transmitter

in the number to Stop bits required. The receiver only re-

quires one Stop bit in a frame, regardless of the setting of the

Stop bit selection bits in the control register. Note that an im-

plicit assumption is made for full duplex USART operatioin

that the framing formats are the same for the transmitter and

receiver.

USART INTERRUPTS

The USART is capable of generating interrupts. Interrupts

are generated on Receive Buffer Full and Transmit Buffer

Empty. Both interrupts have individual interrupt vectors. Two

bytes of program memory space are reserved for each inter-

rupt vector. The two vectors are located at addresses 0xEC

to 0xEF Hex in the program memory space. The interrupts

can be individually enabled or disabled using Enable Trans-

mit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in

the ENUI register.

The interrupt from the Transmitter is set pending, and re-

mains pending, as long as both the TBMT and ETI bits are

set. To remove this interrupt, software must either clear the

ETI bit or write to the TBUF register (thus clearing the TBMT

bit).

The interrupt from the receiver is set pending, and remains

pending, as long as both the RBFL and ERI bits are set. To

remove this interrupt, software must either clear the ERI bit

or read from the RBUF register (thus clearing the RBFL bit).

Baud Clock Generation

The clock inputs to the transmitter and receiver sections of

the USART can be individually selected to come either from

an external source at the CKX pin (port L, pin L1) or from a

source selected in the PSR and BAUD registers. Internally,

the basic baud clock is created from the oscillator frequency

through a two-stage divider chain consisting of a 1–16 (in-

crements of 0.5) prescaler and an 11-bit binary counter. (

Fig-

ure 46) The divide factors are specified through two read/

DS012837-49

FIGURE 45. Framing Formats

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