COP888EB datasheet(55/75 Pages) NSC

55 / 75 page

A/D Converter (Continued)

on for seven clock cycles. If the A/D is in single conversion

mode, the conversion complete signal from the A/D will gen-

erate a power down for the A/D converter and will clear the

ADBSY bit in the ENAD register at the next instruction cycle

boundary. If the A/D is in continuous mode, the conversion

complete signal will restart the conversion sequence by de-

selecting the A/D for one converter clock cycle before start-

ing the next sample. The A/D 8-bit result is immediately

loaded into the A/D result register (ADRSLT) upon comple-

tion. Internal logic prevents transient data (resulting from the

A/D writing a new result over an old one) being read from

ADRSLT.

Inadvertent changes to the ENAD register during conversion

are prevented by the control logic of the A/D. Any attempt to

write any bit of the ENAD Register except ADBSY, while

ADBSY is a one, is ignored. ADBSY must be cleared either

by completion of an A/D conversion or by the user before the

prescaler, conversion mode or channel select values can be

changed. After stopping the current conversion, the user can

load different values for the prescaler, conversion mode or

channel select and start a new conversion in one instruction.

It is important for the user to realize that, when used in differ-

ential mode, only the positive input to the A/D converter is

sampled and held. The negative input is constantly con-

nected and should be held stable for the duration of the con-

version. Failure to maintain a stable negative input will result

in incorrect conversion.

PRESCALER

The A/D Converter (A/D) contains a prescaler option that al-

lows four different clock selections. The A/D clock frequency

is equal to CKI divided by the prescaler value. Note that the

prescaler value must be chosen such that the A/D clock falls

within the specified range. The maximum A/D frequency is

1.67 MHz. This equates to a 600 ns A/D clock cycle.

The A/D converter takes 17 A/D clock cycles to complete a

conversion. Thus the minimum A/D conversion time for the

device is 10.2 µs when a prescaler of 6 has been selected.

The 17 A/D clock cycles needed for conversion consist of 1

cycle at the beginning for reset, 7 cycles for sampling, 8

cycles for converting, and 1 cycle for loading the result into

the A/D result register (ADRSLT). This A/D result register is a

read-only register. The user cannot write into ADRSLT.

The ADBSY flag provides an A/D clock inhibit function, which

saves power by powering down the A/D when it is not in use.

Note: The A/D converter is also powered down when the device is in either

the HALT or IDLE modes. If the A/D is running when the device enters

the HALT or IDLE modes, the A/D powers down and then restarts the

conversion with a corrupted sampled voltage (and thus an invalid re-

sult) when the device comes out of the HALT or IDLE modes.

Analog Input and Source Resistance Considerations

Figure 43 shows the A/D pin model in single ended mode.

The differential mode has a similar A/D pin model. The leads

to the analog inputs should be kept as short as possible.

Both noise and digital clock coupling to an A/D input can

cause conversion errors. The clock lead should be kept

away from the analog input line to reduce coupling. The A/D

channel input pins do not have any internal output driver cir-

cuitry connected to them because this circuitry would load

the analog input signals due to output buffer leakage current.

Source impedances greater than 3 k

Ω on the analog input

lines will adversely affect the internal RC charging time dur-

ing input sampling. As shown in

Figure 43, the analog switch

to the DAC array is closed only during the 7 A/D cycle

sample time. Large source impedances on the analog inputs

may result in the DAC array not being charged to the correct

voltage levels, causing scale errors.

If large source resistance is necessary, the recommended

solution is to slow down the A/D clock speed in proportion to

the source resistance. The A/D converter may be operated

at the maximum speed for R

S less than 3 kΩ. For RS greater

than 3 k

Ω, A/D clock speed needs to be reduced. For ex-

ample, with R

S = 6kΩ, the A/D converter may be operated

at half the maximum speed. A/D converter clock speed may

be slowed down by either increasing the A/D prescaler

divide-by or decreasing the CKI clock frquency. The A/D

minimum clock speed is 100 kHz.

DS012837-18

*The analog switch is closed only during the sample time.

FIGURE 43. A/D Pin Model (Single Ended Mode)

COP888EB датащи(PDF) 55 Page - National Semiconductor (TI)

COP888EB датащи(HTML) 55 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

датащи скачать

ссылки URL